A low-power ADC with compact AGC loop for LR-WPAN receivers

Abstract

This paper presents a novel pipelined analog-to-digital converter (ADC) with a dB-linearity automatic gain control (AGC) loop that exhibits both power and area efficiencies for low-rate wireless personal area network (LR-WPAN) receiver applications. The AGC loop is designed based on feedback architecture for high linearity and a full-digitally control method is proposed to simplify the gain adjusting. The sample-and-hold amplifier less (SHA-less) scheme is employing in ADC design, and moreover, an evaluation-time-sharing technique which combined opamp- and capacitor-sharing is presented for low power consumption and elimination of memory effect. The proposed circuit shows a gain error less than ±0.56 dB in a wide dynamic range of about 70 dB by 2 dB/step and achieves a maximum IIP3, SNDR, SFDR of 16.27 dBm, 41.87 dB, 58.72 dB, respectively. Designed in a 0.18 μm CMOS technology, the proposed circuit has been integrated in the LR-WPAN transceiver. The chip area is as small as 0.94 mm2 and the total power consumption is only 7.62 mW from a 1.8 V single supply.