At-speed Testing Research Articles

A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features

This article proposes practical design techniques to enhance performance and reliability of 1024 GB/s high-bandwidth memory-3 (HBM3). Effective data-bus design methods are applied to transfer data from multi-bank to a data-bus with a sufficient data fetch margin. A symbol-based on-die error-correcting code (OD-ECC) to correct a 16-bit error, bounded by a sub-wordline (WL), and parallelized data-bus inversion (DBI) are implemented. Error check and scrub (ECS) mode and repair capability check (RCC) mode with an internal serial interface are designed to support system reliability, availability, and serviceability (RAS). A memory built-in self-test (MBIST) provides a unified at-speed test with programmability based on test-set units (TUs). A 16 GB HBM3 fabricated in the third generation of the 10 nm class DRAM process achieves a bandwidth up to 1024 GB/s (8 Gb/s/pin) and provides stable operation at a high temperature (e.g., 105 °C) while improving an error detection rate by 92.2%.

A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead

In-situ timing error detection and correction (EDAC) structure is widely adopted in timing-error resilient circuits to reduce the conservative timing guardband induced by process, voltage, and temperature (PVT) variations. However, it introduces the latch-based datapath as well as extra detection and propagation logic, therefore challenges the design-for-testability (DFT) implementation. In this article, we propose a novel DFT-compatible EDAC structure with significant signal control simplification and test-pattern complexity reduction, featuring low area and test overhead. This structure leverages a new scannable EDAC cell (SEDC) which can be configured for timing EDAC in normal mode, or for shift operations as a flip-flop in scan mode. Specifically, the proposed detection logic can be controlled succinctly in scan shift operations and then observed via the global error propagation logic with simple control signal configurations during the test. Therefore, the sophisticated test pattern generation and critical path sensitization are removed. Based on the structure, a shift-based test method is presented to cover the EDAC structure with a low test pattern complexity and test time overheads. As compared with previous works, the proposed SEDC saves 30.5% area, 16.6% power, and 20.3% delay. Besides, our test method cooperating with the proposed EDAC structure reduces <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$149\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$23\times $ </tex-math></inline-formula> static and at-speed test patterns, respectively, together with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$232\times $ </tex-math></inline-formula> static test cycles, and up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25\times $ </tex-math></inline-formula> at-speed test cycles on average, which proves the effectiveness for DFT.

PASTE: FPGA-based Portable At-speed Scan Test Equipment

The increasing integration and complexity of chips driven by Moore’s Law has placed higher demands on chip verification and testing efforts. Automated Test Equipments (ATE) in conjunction with design for testability can effectively screen out faulty chips, but ATE is too costly and can be functionally redundant to be practical for small and medium-sized chip design companies and scientific research in universities. Therefore, in recent years, there has been a lot of research work on FPGA-based low-cost test equipment, but few studies have used the scan test method and have not been able to realize the at-speed test of the chip. In this paper, we propose a portable, low-cost and configurable FPGA-based chip scan test method, which can realize both normal and at-speed test, and can effectively filter the stuck-at faults and transition faults of the chip. We also optimize the test code size via run-length code compression algorithm and achieve a 68.16% compression rate for the test code, which effectively reduces the overall data storage and transmission overhead.

Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs

Monolithic 3-D (M3-D) integration is an emerging technology that offers significant power, performance, and area benefits for an integrated circuit (IC) design. However, a problem with the 3-D power distribution network in such ICs is that it can lead to high power supply noise (PSN) during the capture cycles in at-speed scan testing for transition delay faults. Therefore, the failure of good chips (i.e., yield loss) resulting from the PSN-induced voltage droop is a major concern for M3-D designs. In this article, we first assess the PSN and voltage droop problems and their impact on path delays for at-speed testing of benchmark M3-D designs. Next, we present an analysis framework to identify test patterns that are most likely to lead to yield loss. We describe a test-pattern reshaping solution based on integer linear programming to make appropriate changes to the test patterns that cause yield loss. Simulation results for four M3-D benchmarks highlight the effectiveness of the proposed solution.

Novel Architecture for Logic Test Using Single Cycle Access Structure

Conventional shift-based scan chains have the drawback of peak power consumption which is reduced by the proposed single cycle access test structure for logic test. With the reduction of this power consumption the activity during shift and capture cycles have been achieved. In addition, more accurate circuit behavior can be achieved even at stuck-at and at-speed tests using the proposed methodology. Thereby it accomplishes close proximity to the functional mode during higher frequency operation tests. By using the proposed design minimum number of test cycles can be gained to the existed literature. It is observed that test cycles per net is below 1 for larger designs when tested for simple test pattern generator algorithm without test pattern compression. Has the advantage of autonomous of the plan estimate conjointly gives an extra on-chip investigating flag permeability for each enrols. It is in reverse congruous to the standard full check plans and with a minor improvement existing test design generators and test systems can be utilized conjointly talked about for the arrangement of including built-in self-test (BIST) and gigantic parallel check chains with the proposed plan. The design and implementation of single cycle access test structure for logic test is functionally verified using Vivado. The pre layout and post layout synthesis and its physical design are performed using cadence Genus and Innonus tools respectively, with the optimized area, power, and delay.

Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage

Classical transition delay fault (TDF) model-based delay tests cannot detect small-delay defects (SDDs) properly in many circuits because they do not set the test slack properly to match the size of the tested delay fault. In this article, we propose a new method of using faster-than-at-speed clocks to enhance a classical TDF-based test pattern set and create an optimized SDD test that can detect effective SDDs. We define effective SDDs as SDDs that can immediately fail a circuit and distinguish them from those that grow over time to fail the circuit (reliability defects). The optimized SDD test developed in this article can either target only effective SDDs or also include reliability defects that are close to fail a circuit. In order to improve the SDD test quality, the proposed optimization method uses the recently proposed weighted slack percentage (WeSPer) as the SDD test quality metric to match each pattern with an appropriate test clock speed and then generates the proper masking vector. The optimization method includes a technique for reducing the final pattern count while keeping WeSPer value high. On a set of benchmark circuits, the proposed technique is able to improve the WeSPer value by up to 32.97% (a relative improvement of 60.98%) compared to classical at-speed testing using the same pattern set. This article also discusses the application of this technique on a self-timed circuit that has previously been at-speed tested. The proposed optimization technique improved the SDD test quality from 60% to 69% for preexisting set of test clocks and patterns. Post-silicon test results for the processor are included in this article.

Divide and Compact — Stochastic Space Compaction for Faster-than-at-Speed Test

With shrinking feature sizes detecting small delay faults is getting more and more important. But not all small delay faults are detectable during at-speed test. By overclocking the circuit with several different test frequencies faster-than-at-speed test (FAST) is able to detect these hidden delay faults. If the clock frequency is increased, some outputs of the circuit may not have stabilized yet, and these outputs have to be considered as unknown ([Formula: see text]-values). These [Formula: see text]-values impede the test response compaction. In addition, the number and distribution of the [Formula: see text]-values vary with the clock frequency, and thus a very flexible [Formula: see text]-handling is needed for FAST. Most of the state-of-the-art solutions are not designed for these varying [Formula: see text]-profiles. Yet, the stochastic compactor by Mitra et al. can be adjusted to changing environments. It is easily programmable because it is controlled by weighted pseudo-random signals. But an optimal setup cannot be guaranteed in a FAST scenario. By partitioning the compactor into several smaller ones and a proper mapping of the scan outputs to the compactor inputs, the compactor can be better adapted to the varying [Formula: see text]-profiles. Finding the best setup can be formulated as a set partitioning problem. To solve this problem, several algorithms are presented. Experimental results show that independent from the scan chain configuration, the number of [Formula: see text]-values can be reduced significantly while the fault efficiency can be maintained. Additionally, it is shown that [Formula: see text]-reduction and fault efficiency can be adapted to user-defined goals.

Implementation of ARINC 659 Bus Controller for Space-Borne Computers

As one of the key technologies of Honeywell, the aeronautical radio incorporated (ARINC) 659 bus is popular in current space-borne computers. However, Honeywell does not design ARINC 659 bus controller separately, and there are only a few papers about FPGA-based ARINC 659 bus controllers. Accordingly, to promote the extremely high performance needs of space-borne computers, this paper designs an ARINC 659 bus controller chip which integrates two independent bus interface units (BIUs), one 8-bit MCU, and several peripheral interfaces (i.e., UART, SPI, and I2C). Because the two BIUs are identical and mutually checked, the symmetry problem is emphatically dealt with in the design of this bus controller, and effective timing convergence is realized, which makes the bus controller work reliably and stably. In addition, due to the circuit’s large scale, design for testability (DFT) is also considered. Accordingly, on-chip clock (OCC) and scanning compression test technique are used to realize the at-speed test and shorten the test time, respectively.

At-Speed Scan Test in ASIC Design with On-Chip Clock

At-Speed Scan Test in ASIC Design with On-Chip Clock

An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST

In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

Automation of Test Program Synthesis for Processor Post-silicon Validation

Software-based self-testing (SBST) is introduced for at-speed testing of processors, which is difficult with any of the external testing techniques. Evolutionary approaches are used for the automatic synthesis of SBST programs. However, a number of hard-to-detect faults remain unidentified by these autogenerated test programs. Also, these approaches have considered fault models which have low correlation with the gate-level fault models. This paper presents a greed-based strategy, where the instruction sequences that detect the freshly identified faults are preserved throughout the evolutionary process to identify the hard-to-test faults of the processor. Subsequently, the overall coverage is also improved. A selection probability is estimated from the testability properties of the processor components and assigned to every instruction to accelerate the test synthesis. The range of performance and scalability are comprehensively evaluated on a configurable MIPS processor and a full-fledged 7-stage pipeline SPARC V8 Leon3 soft processor using behavioral fault models. The efficacy of our approach was explained by demonstrating the correlation between behavioral faults and gate-level faults of MIPS processor for the proposed scheme. Experimental results show that improved coverages of 96.32% for the MIPS processor and 95.8% for the Leon3 processor are achieved in comparison with the conventional methods, which have about 90% coverage on the average.

Design for Small Delay Test - A Simulation Study

Early Life Failures (ELFs) are becoming an important reliability issue in state-of-the-art technologies. ELFs can be indicated by Small Delay Faults (SDFs), however, some SDFs may not be detectable even with modern at-speed tests. For these hidden SDFs, Faster-than-at-Speed Test (FAST) provides a solution. However, FAST imposes new challenges on the test method. Unknown logic values (X-values) are a major challenge in FAST, due to the increased frequencies. A special Design-for-FAST architecture relying on an accordingly adjusted scan configuration and a simple, but efficient X-masking scheme can support X-tolerant compaction in the context of FAST. This work analyzes the trade-offs of this concept within the framework of a standard industrial workflow and presents a comprehensive case study. Simulation results indicate that for some designs, the conventional synthesis workflow does not produce optimal circuit behavior under FAST. In these cases, the Design-for-FAST approach can increase the fault efficiency, while at the same time reducing the amount of X-values in the test responses considerably.

Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing

Due to the increase in manufacturing/environmental uncertainties in the nanometer regime, testing digital chips under different operating conditions becomes mandatory. Traditionally, stuck-at tests were applied at slow speed to detect structural defects and transition fault tests were applied at-speed to detect delay defects. Recently, it was shown that certain cell-internal defects can only be detected using at-speed stuck-at testing . Stuck-at test patterns are power hungry, thereby causing excessive voltage droop on the power grid, delaying the test response, and finally leading to false delay failures on the tester. This motivates the need for peak power minimization during at-speed stuck-at testing. In this article, we use input toggle minimization as a means to minimize a circuit’s power dissipation during at-speed stuck-at testing under the Combinational State Preservation scan (CSP-scan) Design-For-Testability (DFT) scheme. For circuits whose test sets are dominated by don’t cares, this article maps the problem of optimal X-filling for peak input toggle minimization to a variant of the interval coloring problem and proposes a Dynamic Programming (DP) algorithm (DP-fill) for the same along with a theoretical proof for its optimality. For circuits whose test sets are not dominated by don’t cares, we propose a max scatter Hamiltonian path algorithm, which ensures that the ordering is done such that the don’t cares are evenly distributed in the final ordering of test cubes, thereby leading to better input toggle savings than DP-fill. The proposed algorithms, when experimented on ITC99 benchmarks, produced peak power savings of up to 48% over the best-known algorithms in literature. We have also pruned the solutions thus obtained using Greedy and Simulated Annealing strategies with iterative 1-bit neighborhood to validate our idea of optimal input toggle minimization as an effective technique for minimizing peak power dissipation during at-speed stuck-at testing.

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC.

A Hybrid Delay Design-for-Testability for Nonseparable RTL Controller-Data Path Circuits

Path delay testing has become crucial nowadays due to the advancement in process technology. Only enhanced scan (ES) among the scan approaches provides a solution to test the path delay fault (PDF) with large area overhead and the long test application time. This paper proposes a hybrid DFT method for nonseparable controller-data path RTL circuits. A snooping system is introduced which reduces the test application time. It performs the PDF testing between the controller and data path, and for the not-Clear control lines in the data path. The proposed method shared primary inputs and outputs to overcome the extra pin. However, the area overhead for the proposed approach is slightly large for the circuit with a small bit-width data path, which reduced drastically by the increase in the bit-width. The proposed approach supports the at-speed testing and is based on the PDF model. The experimental results showed that the proposed approach reduces the area overhead and drastically reduces the test application time in comparison with the enhanced scan (ES) and hierarchical two-pattern testability (HTPT) approach. Moreover, the technique can achieve a fault coverage identical to that achieved by the ES technique.

An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization

Advanced nanometer technologies have led to a drastic increase in operational frequencies resulting in the performance of circuits becoming increasingly vulnerable to timing variations. The increasing process spread in advanced nanometer nodes poses considerable challenges in predicting post-fabrication silicon performance from timing models. Thus, there is a great need to qualify basic building structures on silicon in terms of critical parameters before they could be integrated within a complex System-on-Chip (SoC). The work of this paper presents a configurable circuit and an associated power-aware at-speed test methodology for the purpose of qualifying basic standard cells and complex IP structures to detect the presence of timing faults. Our design has been embedded within test-chips used for the development of the 28 nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The relevant silicon results and analysis validate the proposed power-aware test methodology for qualification and characterization of IPs and provide deeper insights for process improvements.

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill

At-speed testing of deep-submicrometer or nano-scale integrated circuits (ICs) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3-D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation of performance and reliability, as a rise in temperature can introduce an extra delay along paths. As a result, the delay of an otherwise fault-free path may exceed the functional clock period. Such thermal emergencies can thus lead to over-detection and undue yield loss during testing. Their effects will be more severe for small-delay defects (SDDs), which target to sensitize the long paths in a circuit. In this paper, we quantify, for the first time, the impact of thermal emergencies on SDDs and provide a solution to mitigate them. The proposed method is based on: 1) a new thermal-aware (TA) path-selection method, 2) a TA test-ordering method, and 3) an effective scan architecture and a test-application scheme. Experimental results on benchmarks demonstrate that the new method can significantly reduce the number of over-detections of SDDs.

Complex Networks Clustering for Lower Power Scan Segmentation in At-Speed Testing

Complex Networks Clustering for Lower Power Scan Segmentation in At-Speed Testing

Design Flow Allowing the Effective Use of Non-scan and Scan-Based Tests

At speed delay testing is important for embedded systems. Attempts to solve the problems of delay testing only with non-scan or scan-based tests are unsuccessful. There is no need to oppose these tests, but it is necessary to use both taking full advantage of their opportunities. Design flow and the ability to use non-scan and scan-based ATPG, functional test and fault simulation is presented. The goal is to detect as many faults with non-scan at-speed test. The remaining faults are detected with a scan-based test. As a result, there are less of undetected faults and the length of the scan-based test is reduced. The proposed approach provides more flexibility for test generation. Design flow forced the development of new methods for speeding up fault simulation and for more efficient generation of input patterns. Experimental results demonstrate the possibilities of approach.