At-speed Testing Research Articles

What is the statistical method for at-speed testing?

Manufacturing testing becomes increasingly difficult in the nanometer manufacturing region because of the impacts of process variation on path delays. It has been frequently observed from manufacturing testing that different chips exhibit different speed limiting paths; and different set of paths may fail to meet the timing specification for different chips.

Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment

Yield loss caused by excessive power supply noise has become a serious problem in at-speed scan testing. Although X-filling techniques are available to reduce the launch cycle switching activity, their performance may not be satisfactory in the linear-decompressor-based test compression environment. This paper solves this problem by proposing a novel integrated automatic test pattern generation scheme that efficiently and effectively performs compressible low-capture-power X -filling. Related theoretical principles are established, based on which the problem size is substantially reduced. The proposed scheme is validated by benchmark circuits, as well as an industry design in the embedded deterministic test environment.

A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects

Interconnect defects such as weak resistive opens, shorts, and bridges increase the path delay affected by a pattern during manufacturing test but are not significant enough to cause a failure at functional frequency. In this paper, a new faster-than-at-speed method is presented for delay test pattern application to screen small delay defects. Given a test pattern set, the technique groups the patterns into multiple subsets with close path delay distribution and determines an optimal test frequency considering both positive slack and performance degradation due to IR-drop effects. Since, the technique does not increase the test frequency to an extent that any paths exercised at the rated functional frequency may fail, it avoids any scan flip-flop masking. As most semiconductor companies currently deploy compression technologies to reduce test costs, scan-cell masking is highly undesirable for pattern modification as it would imply pattern count increase and might result in pattern regeneration. Therefore, our solution is more practical as the test engineer can run the same pattern set without any changes to the test flow other than the at-speed test frequency.

Optimal Test Margin Computation for At-Speed Structural Test

In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly higher speed than the target frequency required in the field. The additional performance required on the tester is called <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">test</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">margin</i> . There are many good reasons for margin, including voltage and temperature requirements, incomplete test coverage, aging effects, coupling effects, and accounting for modeling inaccuracies. By taking advantage of statistical timing, this paper proposes an optimal method of test margin determination to maximize yield while staying within a prescribed shipped product quality loss limit. If process information is available from the wafer testing of scribe-line structures or on-chip process monitoring circuitry, this information can be leveraged to determine a <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">per-chip</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">test</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">margin</i> which can further improve yield.

Power-aware Test Generation for Reducing Yield Loss Risk in At-Speed Scan Testing

Power-aware X-filling is a preferable approach to avoiding IR-drop-induced yield loss in at-speed scan testing without the need of any circuit modification. However, the effect achieved by previous X-filling methods for reducing launch switching activity may be far from optimal. In addition, some of them are not scalable. This paper proposes a new X-filling method based on the genetic algorithm (GA). Experimental results on benchmark circuits demonstrate the effectiveness and scalability of the new X-filling method for reducing launch switching activity.

Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories

Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.

Droop sensitivity of stuck-at fault tests

In nanometer-scale integrated circuits, simultaneous switching at gates in physical proximity may induce power supply droop, and thereby invoke timing faults, termed as droop faults. During at-speed testing of such chips, two test vectors in a test sequence may excite droop and, thus, cause test invalidation. Fast application of test vectors may be needed for high-speed testing or for built-in self-test systems. The occurrence of droop strongly depends on the sequence of test vectors applied. The effect of droop on fast testing of stuck-at faults is investigated. For combinational circuits, the droop sensitivity of a given test sequence is studied and a method of re-ordering to reduce this effect is proposed. Experimental results on benchmark circuits show that the increase in test length to achieve droop-insensitive re-ordering is low. Droop excitability in full-scan sequential circuits is also studied.

A Decorrelating Design-for-Digital-Testability Scheme for $\Sigma{-}\Delta$ Modulators

This paper presents a novel decorrelating design-for-digital-testability (D3T) scheme for Sigma-Delta modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order Sigma-Delta modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than -5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the D3T scheme has the potential to test moderate nonlinearity. The proposed D3T scheme has the advantages of achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.

Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity

As chip integration continues to increase and technology scaling is forcing the operating voltage to decrease, modern designs have become more susceptible to supply voltage noise. However, even with a well designed power distribution network, modern at-speed test pattern generation techniques do not consider the maximum current throughput the network will be able to provide. As a result, conventional transition delay fault pattern generation tends to create a number of patterns that cause higher-than-average functional switching, which may cause timing and/or functional failures during test. In this paper, we propose a flow that incorporates the layout information and the locality of the switching activity during pattern generation to provide insight into the amount of tolerable switching. This will prevent both IR-drop related hot-spots and under-utilization of the chip since the switching activity can be evenly spread across the design. The results presented in this paper show significant improvement over our previous flow without negatively impacting fault coverage and pattern count.

Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test

Scan chain division has been successfully used to control shift power by enabling mutually exclusive flip-flops at different times during the scan cycle. However, to control capture power without losing transition fault coverage during at-speed scan test, the existing automatic test pattern generation (ATPG) flows need to be modified. In this paper, we present a novel scan chain division algorithm that analyzes the signal dependencies and creates the circuit partitions such that both shift and capture power can be reduced when using the existing ATPG flows. This novel algorithm has been designed for the broadside test application strategy, and a technique for employing partial scan when dividing the scan chains is also proposed.

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

This paper describes the design-for-testability (DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test (BIST) circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops (PLL) to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation (ATPG) and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing (HVM) DFT plan to meet high quality test goals as well as slow test power consumption and cost.

Systematic Software-Based Self-Test for Pipelined Processors

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models

This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.

Structure Design and Optimization of 2-D LFSR-Based Multisequence Test Generator in Built-In Self-Test

This paper addresses the optimization of very large scale integration testing systems, specifically the structure design and optimization of a built-in self-test (BIST) design based on two-dimensional (2D) linear feedback shift registers (LFSRs). The 2D LFSRs can generate both precomputed test patterns (for detecting random-pattern-resistant faults) and random patterns (for detecting random-pattern-detectable faults) and have the advantages of high fault coverage and at-speed testing. To guarantee solutions, it is necessary and desirable to generate subsequences of the precomputed test patterns through the 2D LFSRs, where these subsequences retain the order of the test patterns, particularly for testing sequential circuits. For the design and optimization of the 2D LFSRs, the following two problems need to be solved: 1) the good partitioning of the precomputed test patterns into disjoint subsequences in order to achieve a minimal hardware and 2) the structure design and optimization of the 2D LFSRs to generate the test patterns in each partitioned subsequence. The optimization of the 2D LFSRs is modeled as an integer program (a logic optimization model) that determines the coefficients of the recursive Boolean equations that govern the generation of the test patterns. For a sequence of the test patterns, this model finds the minimal-hardware implementation of the 2D LFSRs. This logic optimization model can be applied to both test-per-scan (serial BIST) and test-per-clock (parallel BIST). This paper presents how this model is embedded in a heuristic framework to partition the test patterns into subsequences from the configurable 2D LFSRs. The testing hardware is small as the configurable architecture allows the tester to incrementally generate the precomputed test patterns by modification to the feedback of the 2D LFSRs. Results of benchmark circuits show that significant hardware reduction and higher fault coverage are achieved. The resulting multisequence test generator is a regular structure and is easy to implement. The logic optimization model is applicable to both completely and partially specified test patterns and can be adopted for other LFSR-based structure design and optimization.

Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors

In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency, that is, it completely avoids the error masking. Moreover, the proposed method has no performance degradation (adds only observation points) and enables at-speed testing.

Small-delay defect detection in the presence of process variations

Interconnect-based defects such as partial opens are becoming more prevalent in nanoscale designs. These are latent defects that affect circuit reliability and can be modeled as small-delay defects. Detecting such defects therefore requires faster than at-speed test clocks. In the paper we analyze the uncertainty introduced by process variations in detecting these defects. We propose new path selection algorithms that increase the probability of defect detection by taking into account the variability in path delays. Our results show that the new technique detects much smaller defects than the traditional approach of selecting the longest paths for test.

Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy

This paper discusses an automated method to divide scan chains into multiple scan segments that are suitable for power-constrained at-speed testing using the skewed-load test application strategy. By dividing a circuit into multiple partitions, which can be tested independently, both power during shift and power during capture can be controlled. Despite activating one partition at a time, we show how through conscious construction of scan segments, high transition fault coverage can be achieved, while reducing test time of the circuit and employing third party test generation tools.

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However, at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity. This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage loss, and additional design effort.

Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation

A transition fault model is described, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences. At-speed test application allows a circuit to be tested under its normal-operation conditions. However, fault simulation and test generation for standard transition faults become significantly more complex due to the need to handle faulty signal transitions that span multiple clock cycles. As a result, each transition fault needs to be considered multiple times, with multiple sizes of the extra delay on the faulty line. The proposed fault model alleviates this shortcoming by introducing unspecified values into the faulty circuit when fault effects may occur, thus allowing faults of all possible sizes to be encompassed in a single fault. Fault detection potentially occurs when an unspecified value reaches a primary output. Pessimistic, optimistic, and versions of the fault model and corresponding fault coverages are defined. If a single fault coverage is to be computed, the pessimistic one provides the lowest fault coverage. By using the optimistic or random version, it is possible to obtain a range of possible fault coverages that is analogous to the range of sizes of transition faults. For certain applications, it is also possible to include more than one version of every fault in a single set of target faults and to compute a single fault coverage. Experimental results of fault simulation and test generation are presented to demonstrate the behavior of the model and to compare it with other fault models.

Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols

Variations in crosstalk is an added source of delay and glitch faults in System on Chips built with deep sub-micron technology, especially in chips using wide and long buses. Many of these faults, in such sub-micron chips, may only appear when the chip works at normal operating speed. These crosstalk-induced faults are more serious in systems built with Globally Asynchronous Locally Synchronous principles. The authors propose efficient methods for at-speed testing of such faults in asynchronous links connecting, for example, two switches/routers of an network-on-chip communication infrastructure. The proposed delay test method has the property that all faulty chips are identified but some good chips may also be characterised as faulty with a small probability. The authors give an analytical analysis regarding this probability as a function of probability of delay fault and number of applied test instances. A simple and pure digital BIST hardware is also proposed, which is represented at Register Transfer level to implement the delay test method. A method is also proposed for detecting glitches on control lines in a handshaking-based communication link; thereafter it is shown how the method can be extended for detecting glitch faults on data lines. The proposed test methods for detecting delays and glitches provide a complete scheme for detection of crosstalk-induced faults in links in an on-chip communication infrastructure using asynchronous handshaking communication protocols.