Abstract

Interconnect-based defects such as partial opens are becoming more prevalent in nanoscale designs. These are latent defects that affect circuit reliability and can be modeled as small-delay defects. Detecting such defects therefore requires faster than at-speed test clocks. In the paper we analyze the uncertainty introduced by process variations in detecting these defects. We propose new path selection algorithms that increase the probability of defect detection by taking into account the variability in path delays. Our results show that the new technique detects much smaller defects than the traditional approach of selecting the longest paths for test.

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