Abstract
As one of the key technologies of Honeywell, the aeronautical radio incorporated (ARINC) 659 bus is popular in current space-borne computers. However, Honeywell does not design ARINC 659 bus controller separately, and there are only a few papers about FPGA-based ARINC 659 bus controllers. Accordingly, to promote the extremely high performance needs of space-borne computers, this paper designs an ARINC 659 bus controller chip which integrates two independent bus interface units (BIUs), one 8-bit MCU, and several peripheral interfaces (i.e., UART, SPI, and I2C). Because the two BIUs are identical and mutually checked, the symmetry problem is emphatically dealt with in the design of this bus controller, and effective timing convergence is realized, which makes the bus controller work reliably and stably. In addition, due to the circuit’s large scale, design for testability (DFT) is also considered. Accordingly, on-chip clock (OCC) and scanning compression test technique are used to realize the at-speed test and shorten the test time, respectively.
Highlights
Backplane bus is a communication network used to connect various functional plug-ins in a computer system
The aeronautical radio incorporated (ARINC) 659 standard proposed by Honeywell was originally used in the SAFEbusTM of Boeing 777’s aircraft information management system (AIMS) [9]
The space-borne computers used in space explorations such as the highly reliable layered system (HRLS) of NASA [11] and the Shenzhou spacecraft of CASC [12], began to adopt the ARINC 659 bus
Summary
Backplane bus is a communication network used to connect various functional plug-ins in a computer system. The ARINC 659 bus has become the most effective way to improve the management and data processing ability of current aerospace electronic system, and it is a hot spot in the development of space-borne computer bus [9,10,11,12,13,14,15]. The scale of ARINC 659 bus controller chip is usually very large, the DFT problem needs to be paid more attention. This paper designs an ARINC 659 bus controller circuit, first to fill the gap in the design of the corresponding chip, second to improve the certainty and fault tolerance of space-borne computers by solving some key technologies, and third, to provide a novel architecture for ARINC 659 bus controller.
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
