Asynchronous Circuits Research Articles

ПРИМЕНЕНИЕ АСИНХРОННЫХ СХЕМ ДЛЯ ПОВЫШЕНИЯ ЗАЩИТЫ ОТ АТАК ПО СТОРОННИМ КАНАЛАМ

The aim of this study is to analyze the use of asynchronous circuits to improve the security of information systems against side-channels attacks, which are means of obtaining unauthorized access to confidential data and performing unauthorized actions in the system. Side-channels attacks are fundamentally different as compared with a cryptographic analysis and an exploitation of software errors in their focus on the hardware of the system under attack. Integrated circuits unintentionally create electromagnetic signals during their operation and have a number of performance characteristics that can be investigated by an attacker and therefore become the sources of information leakage, i.e., side-channels. The security of modern information systems cannot be fully ensured without increasing resistance to such attacks. One of the methods to counter side-channel attacks is the use of asynchronous circuits, which main distinguishing feature is the refusal from the use of a global clock signal to synchronize individual elements of an integrated circuit in favour of local synchronization provided by the "handshake" mechanism. Integrated circuits designed using asynchronous circuitry have a number of unique benefits that make it possible to effectively resist side-channel attacks, such as timing attacks and attacks with using power consumption analysis. This paper presents a classification of side-channels attacks, describes asynchronous circuits and their properties that increase their resistance to certain types of side-channels attacks, and provides examples that clearly show the increase in the protection of information systems with the asynchronous circuits.

Investigation of asynchronous pipeline circuits based on bundled-data encoding: Implementation styles, behavioral modeling, and timing analysis

As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scaling capacity under supply voltage variations. In most practical asynchronous circuits, a pipeline forms the micro-architecture backbone, and its characteristics play a vital role in determining the overall circuit performance. In this paper, we investigate a series of typical asynchronous pipeline circuits based on bundled-data encoding, spanning different handshake signaling protocols such as 2-phase (micropipeline, Mousetrap, and Click), 4-phase (simple, semi-decoupled, and fully-decoupled), and single-track (GasP). An in-depth review of each selected circuit is conducted regarding the handshaking and data latching mechanisms behind the circuit implementations, as well as the analysis of its performance and timing constraints based on formal behavior models. Overall, this paper aims at providing a survey of asynchronous bundled-data pipeline circuits, and it will be a reference for designers interested in experimenting with asynchronous circuits.

Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism

Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism

An Intelligent Model for DDoS Attack Detection and Flash Event Management

Distributed Denial of Service (DDoS) attacks are the foremost security concerns on the Internet. DDoS attacks and a similar occurrence called Flash Event (FE) signify anomalies in the normal network traffic, requiring intelligent interventions. This study presents the design and implementation of an intelligent model for the detection of application-layer DDoS attacks and the prevention of service degradations during FE. A Multi-Layer Perceptron (MLP) classifier was used for detecting DDoS attacks on application servers. The FE management system consists of asynchronous processing of requests on a First-In, First-Out (FIFO) basis. A demo application was set up wherein HTTP flood attack was launched and a Flash Event was simulated. The experimental results clearly show that the MLP classifier in comparison with other machine learning classifiers performs best in terms of speed and accuracy. Also, the evaluation of the FE management system shows a great reduction in service degradation. This reflects that the designed model is capable of averting service unavailability on the web.

A horizontally scalable online processing system for trigger-less data acquisition

The vast majority of high energy physics experiments rely on data acquisition and hardware-based trigger systems performing a number of stringent selections before storing data for offline analysis. The online reconstruction and selection performed at the trigger level are bound to the synchronous nature of the data acquisition system, resulting in a trade-off between the amount of data collected and the complexity of the online reconstruction performed. Exotic physics processes, such as long-lived and slow-moving particles, are rarely targeted by online triggers as they require complex and nonstandard online reconstruction, usually incompatible with the time constraints of most data acquisition systems. The online trigger selection can thus impact as one of the main limiting factors to the experimental reach for exotic signatures. Alternative data acquisition solutions based on the continuous and asynchronous processing of the stream of data from the detectors are therefore foreseeable as a way to extend the experimental physics reach. Trigger-less data readout systems, paired with efficient streaming data processing solutions, can provide a viable alternative. In this document, an end-to-end implementation of a fully trigger-less data acquisition and online data processing system is discussed. An easily scalable and deployable implementation of such an architecture is proposed, based on open-source distributed computing frameworks capable of performing asynchronous online processing of streaming data. The proposed schema can be suitable for deployment as a fully integrated data acquisition system for small-scale experimental apparatus, or to complement the trigger-based data acquisition systems of larger experiments. A muon telescope setup consisting of a set of gaseous detectors is used as the experimental development testbed in this work, and a fully integrated online processing pipeline deployed on cloud computing resources is implemented and described.

Heterocycles: Synthesis, Catalysis, Sustainability, and Characterization

Null convention logic (NCL) is a good design approach for constructing a low-power and high-speed asynchronous system. However, NCL has a higher transistor count with a dual-rail structure, especially for large-scale circuits. To save NCL dual-rail overhead, we present an NCL dual-rail/single-rail hybrid system in which single-rail synchronous combinational logic is used between two NCL dual-rail registers. In addition, a 4-bit dual-rail/single-rail hybrid arithmetic logic unit (ALU) and a 4-bit dual-rail ALU are designed to compare performance. To achieve a faster speed, the operation logics in the hybrid ALU adopt transmission gates (TGs). Compared with the 4-bit NCL dual-rail ALU, the 4-bit hybrid ALU (OR operation) has advantages in smaller transistor count (reduced by 14.8%), smaller layout area (reduced by 0.16 mm2), lower power consumption (reduced by 47%), lower delay (reduced by 0.19 ns), and less effect of process/voltage/temperature (PVT) variations. Moreover, the 4-bit NCL dual-rail ALU is optimized with embedded registers in terms of transistor count (reduced by 4%), TASY (reduced by 0.18 ns), and power dissipation (reduced by 0.1 mW).

A dual-rail/single-rail hybrid system using null convention logic circuits

Null convention logic (NCL) is a good design approach for constructing a low-power and high-speed asynchronous system. However, NCL has a higher transistor count with a dual-rail structure, especially for large-scale circuits. To save NCL dual-rail overhead, we present an NCL dual-rail/single-rail hybrid system in which single-rail synchronous combinational logic is used between two NCL dual-rail registers. In addition, a 4-bit dual-rail/single-rail hybrid arithmetic logic unit (ALU) and a 4-bit dual-rail ALU are designed to compare performance. To achieve a faster speed, the operation logics in the hybrid ALU adopt transmission gates (TGs). Compared with the 4-bit NCL dual-rail ALU, the 4-bit hybrid ALU (OR operation) has advantages in smaller transistor count (reduced by 14.8%), smaller layout area (reduced by 0.16 mm2), lower power consumption (reduced by 47%), lower delay (reduced by 0.19 ns), and less effect of process/voltage/temperature (PVT) variations. Moreover, the 4-bit NCL dual-rail ALU is optimized with embedded registers in terms of transistor count (reduced by 4%), TASY (reduced by 0.18 ns), and power dissipation (reduced by 0.1 mW).

Mamba: a systematic software solution for beamline experiments at HEPS.

To cater for the diverse experiment requirements at the High Energy Photon Source (HEPS) with often limited human resources, Bluesky was chosen as the basis for our software framework, Mamba. In our attempt to address Bluesky's lack of integrated graphical user interfaces (GUIs), command injection with feedback was chosen as the main way for the GUIs to cooperate with the command line interface; a remote-procedure-call service is also provided, which covers functionalities unsuitable for command injection, as well as pushing of status updates. In order to fully support high-frequency applications like fly scans, Bluesky's support for asynchronous control is being improved; furthermore, to support high-throughput experiments, Mamba Data Worker is being developed to cover the complexity in asynchronous online data processing for these experiments. To systematically simplify the specification of metadata, scan parameters and data-processing graphs for each type of experiment, an experiment parameter generator will be developed; experiment-specific modules to automate preparation steps will also be made. The integration of off-the-shelf code in Mamba for domain-specific needs is under investigation, and Mamba GUI Studio is being developed to simplify the implementation and integration of GUIs.

An Asynchronous Bundled-Data Barrel Shifter Design That Incorporates a Deterministic Completion Detection Technique

A design for an asynchronous bundled-data barrel shifter that incorporates a deterministic completion detection circuitry is proposed. A bundled-data asynchronous circuit is inherently free from challenges associated with clock signals, but it is devoid of information pertaining to propagation delay through the circuit. An obvious solution is to produce the acknowledge signal at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta $ </tex-math></inline-formula> delay units after the arrival of the request signal, where <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta $ </tex-math></inline-formula> is the maximum propagation delay through the circuit. However, similar to synchronous circuits, such bundle-data asynchronous approach does not take advantage of times where the propagation delay through the circuit is less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\delta $ </tex-math></inline-formula> . This brief proposes a design for a deterministic completion detection scheme for an asynchronous bundled-data barrel shifter. Once the request signal is active, the shifting operation begins, and the acknowledge signal is generated after a delay that matches the actual shifting delay associated with the shift amount using a deterministic completion detection scheme. The shifter can reduce the idle time between the time its output is ready and the start of the next shift cycle by using a deterministic completion detection circuit. In this brief, the proposed design of the asynchronous barrel shifter and its average delay is analyzed. Its performance is also compared against its synchronous counterpart.

Data Partitioning and Asynchronous Processing to Improve the Embedded Software Performance on Multicore Processors

Nowadays, ensuring information security is extremely inevitable and urgent. We are also witnessing the strong development of embedded systems, IoT. As a result, research to ensure information security for embedded software is being focused. However, studies on optimizing embedded software on multi-core processors to ensure information security and increase the performance of embedded software have not received much attention. The paper proposes and develops the embedded software performance improvement method on multi-core processors based on data partitioning and asynchronous processing. Data are used globally to be retrieved by any threads. The data are divided into different partitions, and the program is also installed according to the multi-threaded model. Each thread handles a partition of the divided data. The size of each data portion is proportional to the processing speed and the cache size of the core in the multi-core processor. Threads run in parallel and do not need synchronization, but it is necessary to share a general global variable to check the executing status of the system. Our research on embedded software is based on data security, so we have tested and assessed the method with several block ciphers like AES, DES, etc., on Raspberry PI3. The average performance improvement rate achieved was 59.09%.

Deep Learning with Multisource Data Fusion in Electricity Internet of Things for Electricity Price Forecast

More and more IoT (Internet of Thing) devices have been connected to our lives in recent years, making life more convenient. Many countries are also making use of Internet of Thing technology to carry out intelligent electricity network reform. One of the reform goals is balancing the supply and demand of electricity, which has become a top priority. Balancing electricity supply and demand through real-time electricity prices has become an effective way. However, using traditional machine learning models for real-time electricity price prediction requires complex feature engineering, and the results are not satisfactory. Also, the mainstream fusion methods use data-level fusion, which will put very high pressure on communication bandwidth and computer resources. In this paper, an LSTM- (long short-term memory-) based decision level fusion of multisource data is proposed and applied for real-time electricity price prediction on actual electricity price datasets. The method solves the difficulties of traditional machine learning models in dealing with complex nonlinear problems. It achieves local asynchronous processing of multisource data through decision-level fusion, reducing the requirement for bandwidth resources and providing perfect results in real-time electricity price prediction. The experimental results show that the prediction accuracy of the decision fusion prediction model based on LSTM is higher than that of the linear regression algorithm.

Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook

The synchronous design paradigm dominates today&#x2019;s semiconductor industry. However, this clocked approach is facing major challenges with today&#x2019;s high-speed, low-power design expectations, using processes with ever-increasing physical level variability. Several clock related issues surface in designs operating at higher frequencies, which make clock management increasingly difficult. Quasi-delay insensitive (QDI) asynchronous (clockless) designs have proved to be effective in circumventing the major limiting factors associated with the clocked designs. NULL Convention Logic (NCL) is one such QDI asynchronous design paradigm, which presents itself as a promising alternative to conventional synchronous circuits and has already found numerous commercial applications due to its low power, robust architecture, and ease of design reuse. This paper presents the evolution of NCL based asynchronous paradigm over the past two decades, primarily focusing on existing fundamental research in NCL design automation, spanning over NCL synthesis, optimization, testing, and verification. The methods are systematically analyzed to determine their limitations and future research directions.

RTL Conversion Method From Pipelined Synchronous RTL Models Into Asynchronous Ones

In this paper, we propose a conversion method from pipelined synchronous Register Transfer Level (RTL) models into pipelined asynchronous RTL models with bundled-data implementation. To know data-path resources controlled by each pipeline stage, the proposed method generates a control data flow graph (CDFG) from synchronous RTL models. After generating the CDFG, the proposed method generates asynchronous RTL models by analyzing each pipeline stage on the CDFG, assigning asynchronous control modules, and connecting the control modules to the data-path resources. In addition, we also propose optimization methods during the conversion. In the experiment, we converted four pipelined synchronous RTL models into pipelined asynchronous ones. In addition, we performed logic synthesis for the converted asynchronous RTL models to check the quality of the asynchronous RTL models. The synthesized asynchronous circuits without the optimization methods could reduce the energy consumption by 1.47&#x0025; on average compared to synchronous circuits. Moreover, the optimization methods could reduce the energy consumption by 15.12&#x0025; on average compared to synchronous circuits. Furthermore, the optimization methods reduced the energy consumption by up to 34.72&#x0025; compared to asynchronous circuits without the optimization methods.

An ASIC Architecture With Inter-Chip Networking for Individual Control of Adaptive-Metamaterial Cells

In this paper, the architecture of an application-specific integrated circuit for adaptive metasurfaces is presented. The architecture allows scalable networking over large metasurfaces and reconfiguration of each unit-cell with unique complex impedance settings, for adjusting metasurface electromagnetic performance. The one-chip-design metasurface array, includes self-initialization/addressing, configuration-packet routing, and network adaptation for fault-tolerant dynamic metasurfaces. An asynchronous design is adopted for power efficiency and high scalability, whereas speed is enhanced through multilevel pipelining. The ability to dynamically form reconfigurable networks in conjunction with the clockless operation helps the metasurface to cover arbitrary physical shapes, implemented on both rigid or flexible substrates. The architecture is validated through transistor-level simulations of the complete design implemented in a commercially available process. Then, a variety of scalable and/or flexible networks are presented, exploiting the strengths offered by the architecture, to demonstrate its capabilities and estimated performance. The demonstrated results of the architecture and its networking capabilities, allow the realization of chip-to-chip programmability of metasurfaces with up to 2¹⁸ ASICs. The individual ASICs can be reconfigured in 2 &#x03BC;s and consume only 342 &#x03BC;W of static power.

Energy-Efficient Massive MIMO for Federated Learning: Transmission Designs and Resource Allocations

This work proposes novel synchronous, asynchronous, and session-based designs for energy-efficient massive multiple-input multiple-output networks to support federated learning (FL). The synchronous design relies on strict synchronization among users when executing each FL communication round, while the asynchronous design allows more flexibility for users to save energy by using lower computing frequencies. The session-based design splits the downlink and uplink phases in each FL communication round into separate sessions. In this design, we assign users such that one of the participating users in each session finishes its transmission and does not join the next session. As such, more power and degrees of freedom will be allocated to unfinished users, resulting in higher rates, lower transmission times, and hence, higher energy efficiency. In all three designs, we use zero-forcing processing for both uplink and downlink, and develop algorithms that optimize user assignment, time allocation, power, and computing frequencies to minimize the energy consumption at the base station and users, while guaranteeing a predefined maximum execution time of each FL communication round.

Real-Time Asynchronous Information Processing in Distributed Power Systems Control

Centralized power system algorithms are gradually augmented and substituted with distributed counterparts, where timely updated asynchronous information processing is critical for real-time implementation. This paper presents two methods to achieve the desired real-time performance. Distributed sequencing method simulates a synchronous system on an asynchronous network using a distributed logical vector clock. The second method, adaptive asynchronous processing, handles asynchrony at each iteration step through adaptive dynamics of the network agents. Necessity of the developed methods is discussed based on the specific requirements of the communication network in terms of algorithm accuracy, network size and time-varying message delays. A case study on the distributed power system state estimation for networked microgrids is presented to validate the developed methods implementing industrial publish/subscribe protocols. The results demonstrate that the developed information processing methods can be efficiently applied for real-world industrial implementation.

ICS: Total Freedom in Manual Text Classification Supported by Unobtrusive Machine Learning

We present the Interactive Classification System (ICS), a web-based application that supports the activity of manual text classification. The application uses machine learning to continuously fit automatic classification models that are in turn used to actively support its users with classification suggestions. The key requirement we have established for the development of ICS is to give its users total freedom of action: they can at any time modify any classification schema and any label assignment, possibly reusing any relevant information from previous activities. We investigate how this requirement challenges the typical scenarios faced in machine learning research, which instead give no active role to humans or place them into very constrained roles, e.g., on-demand labeling in active learning processes, and always assume some degree of batch processing of data. We satisfy the &#x201C;total freedom&#x201D; requirement by designing an unobtrusive machine learning model, i.e., the machine learning component of ICS as an unobtrusive observer of the users, that never interrupts them, continuously adapts and updates its models in response to their actions, and it is always available to perform automatic classifications. Our efficient implementation of the unobtrusive machine learning model combines various machine learning methods and technologies, such as hash-based feature mapping, random indexing, online learning, active learning, and asynchronous processing.

HARMS: A Hardware Acceleration Architecture for Real-Time Event-Based Optical Flow

Event-based vision sensors produce asynchronous event streams with high temporal resolution based on changes in the visual scene. The properties of these sensors allow for accurate and fast calculation of optical flow as events are generated. Existing solutions for calculating optical flow from event data either fail to capture the true direction of motion due to the aperture problem, do not use the high temporal resolution of the sensor, or are too computationally expensive to be run in real time on embedded platforms. In this research, we first present a faster version of our previous algorithm, ARMS (Aperture Robust Multi-Scale flow). The new optimized software version (fARMS) significantly improves throughput on a traditional CPU. Further, we present hARMS, a hardware realization of the fARMS algorithm allowing for real-time computation of true flow on low-power, embedded platforms. The proposed hARMS architecture targets hybrid system-on-chip devices and was designed to maximize configurability and throughput. The hardware architecture and fARMS algorithm were developed with asynchronous neuromorphic processing in mind, abandoning the common use of an event frame and instead operating using only a small history of relevant events, allowing latency to scale independently of the sensor resolution. This change in processing paradigm improved the estimation of flow directions by up to 73% compared to the existing method and yielded a demonstrated hARMS throughput of up to 1.21 Mevent/s on the benchmark configuration selected. This throughput enables real-time performance and makes it the fastest known realization of aperture-robust, event-based optical flow to date.

Design and Implementation of Asynchronous Processor on FPGA

Low-power and fault-tolerant features for microprocessors have been recognized as two of the greatest concerns in applications for edge devices. In this study, we propose asynchronous circuit design techniques for field-programmable gate arrays (FPGA) that can fundamentally overcome the drawbacks of conventional synchronous circuit designs. We used commercial FPGAs and implemented an asynchronous MSP430 microprocessor using the proposed technique. We also introduce an interfacing architecture between the synchronous block memory and asynchronous core to support the congeniality of the commercial embedded processor and the asynchronous core. Furthermore, we analyze a compiler for MSP430 and adapt its result to achieve a high-level development environment for asynchronous MSP430. The experimental results showed that the asynchronous MSP430 consumes 62.3% less power than its synchronous counterpart and has significant fault tolerance compared to the synchronous MSP430 under unstable supply voltage conditions. Additionally, the asynchronous MSP430 emitted 13% less electromagnetic noise at the working frequency.

Defining the speed independence of the Boolean asynchronous systems

A discrete time Boolean asynchronous system consists in a function Φ : {0, 1}n→ {0, 1}nwhich iterates its coordinates Φ1, ..., Φnindependently of each other. The durations of computation of Φ1, ..., Φnare supposed to be unknown. The analysis of such systems has as main challenge characterizing their dynamics in conditions of uncertainty. For this, a very cited classical paper is [1], where the fundamental concept of speed independence is introduced. The point is, like in most of these cases, that the engineers receive from such a work intuition, combined with a certain lack of rigor. Our aim is to try a mathematical reinforcement of the Muller’s theory of the asynchronous circuits, which should be a modest homage, over time, to its authors.A list of models used in asynchronous systems theory is given in [3]. The mathematical tools used in this analysis may be found in [2].