Abstract
Null convention logic (NCL) is a good design approach for constructing a low-power and high-speed asynchronous system. However, NCL has a higher transistor count with a dual-rail structure, especially for large-scale circuits. To save NCL dual-rail overhead, we present an NCL dual-rail/single-rail hybrid system in which single-rail synchronous combinational logic is used between two NCL dual-rail registers. In addition, a 4-bit dual-rail/single-rail hybrid arithmetic logic unit (ALU) and a 4-bit dual-rail ALU are designed to compare performance. To achieve a faster speed, the operation logics in the hybrid ALU adopt transmission gates (TGs). Compared with the 4-bit NCL dual-rail ALU, the 4-bit hybrid ALU (OR operation) has advantages in smaller transistor count (reduced by 14.8%), smaller layout area (reduced by 0.16 mm2), lower power consumption (reduced by 47%), lower delay (reduced by 0.19 ns), and less effect of process/voltage/temperature (PVT) variations. Moreover, the 4-bit NCL dual-rail ALU is optimized with embedded registers in terms of transistor count (reduced by 4%), TASY (reduced by 0.18 ns), and power dissipation (reduced by 0.1 mW).
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