Assertion Coverage Research Articles

A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller

The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method is no longer applicable. This paper proposes a comprehensive and efficient verification testbench based on the SystemVerilog language and universal verification methodology (UVM) for an instruction Cache (I-Cache) controller. Corresponding testcases are designed for each feature of the I-Cache controller and automatically executed using a python script on an electronic design automation (EDA) tool. After simulating a large number of testcases, the statistics reveal that the module’s code coverage is 99.13%. Additionally, both the function coverage and the assertion coverage of the module reach 100%. Our results demonstrate that these coverage metrics meet the requirements and ensure the thoroughness of function verification. Furthermore, the established verification testbench exhibits excellent scalability and reusability, making it easily applicable to higher-level verification scenarios.

Verification of UART and I2C Protocols Using System Verilog

Design Verification in VLSI is the most important step in the product development process. It aims to confirm that the system designed meets with the standards and requirements of the system. Verification is the process of checking whether the designed system performs all the required functionality specified in the design by writing the test bench or verification environment that contains group of classes and modules which generates input stimulus to the system and the output from that design is compared with the expected output. A communication system has set of roles those are called protocols. UART is a serial communication protocol that is used when only two devices are needed to communicate and it uses peer to peer topology. I2C stands for Inter Integrated Circuit used for communication between master and slave in which more than one slave devices or memory can be connected to a master device. System Verilog has been primarily used for the verification purposes in VLSI because it has the features of Hardware Description Languages such as Verilog and VHDL, C and C++ and functional coverage, assertion coverage, constrained randomization and supports OOPs concepts.

HARM: A Hint-Based Assertion Miner

This article presents HARM, a tool to generate linear temporal logic (LTL) assertions starting from a set of user-defined hints and the simulation traces of the design under verification (DUV). The tool is agnostic with respect to the design from which the trace was generated, thus the DUV source code is not necessary. The user-defined hints involve LTL templates, propositions, and ranking metrics that are exploited by the assertion miner to reduce the search space and improve the quality of the generated assertions. This way, the tool supports the work of the verification engineer by including his/her insights in the process of automatically generating assertions. The experimental results show real improvements with respect to the state-of-the-art in terms of assertion coverage and scalability.

Design and Assertion Based Verification of RISC-V Processor Subsystems

RISC-V is an open, free standard architecture. As its open-source architecture, it can be used in multiple applications like embedded processors, IoT, artificial intelligence, machine learning, military and defense applications. The parameters like throughput, performance, high speed etc., become essential in designing processor architecture. Pipelining is one such unique feature supported by RISC-V ISA, which basically involves the execution of multiple instructions in single cycle. This feature helps in improving the performance of the processor architecture. RISC-V ISA supports five stages of pipelining they are instruction fetch, instruction decode, execute, memory and write-back stage. The work covered in this paper involves the design and implementation of the subsystems of the RISC-V ISA which are present in different stages of pipeline architecture. The subsystems included in this work are Floating Point Unit (FPU) of Execute stage, Branch Prediction Unit (BPU) of instruction fetch stage, Forwarding Unit of execution stage, Operand Logic of decode stage and Floating-Point register file of Write-back stage. These subsystems are designed using Verilog Hardware Description Language in Xilinx ISE. Followed by the implementation the verification of the floating-point unit and the forwarding unit is performed using System Verilog Assertions in QuestaSim. The Assertion coverage report for the same is extracted.

Assertion Ranking Using RTL Source Code Analysis

We present a systematic and efficient ranking method to quantify the goodness of an assertion. We model dependencies among design variables as a directed graph called a variable dependency graph . We define assertion importance and assertion complexity metrics and use the dependency graph to algorithmically compute those two metrics. We repurpose an assertion coverage algorithm from the literature to form a statement-coverage-based ranking as our baseline. We compare our assertion ranking both qualitatively and quantitatively to this baseline. We demonstrate that our ranking is computationally more efficient than statement-coverage-based ranking and takes up to $4366\times $ less computation time. We identify the potential design intents that each ranking prioritizes. We also discuss at length the effect of those prioritizations on the rank agreement and the bug detection ability of the top-ranked assertions according to the two rankings. Finally, we provide a comprehensive ranking for a set of assertions by combining our ranking and the statement-coverage-based ranking.

English

This paper mainly deals with the study of Serial Peripheral Interface and logical Implementation through RTL, Synthesis and Simulation by making Test benches of various modules involved using Universal Verification Methodology. It is done with the help of Questasim 10.0b software. Further, output in both Batch and GUI Mode has been observed and discussed. Various test cases of SPI Protocol are taken into consideration, functional coverage, code coverage, and assertion coverage has been verified by synthesis of various blocks involved in top level architecture of SPI.

Functional verification of I2C core using SystemVerilog

The verification phase carries an important role in design cycle of a System on Chip (SoC). A verification environment may be prepared using SystemVerilog without using any particular methodology but that will be different for every variation of the design. There are various verification methodologies out of which Universal Verification Methodology (UVM) is the state-ofthe-art and widely preferred by the verification industry worldwide, as the verification environment created using UVM is reusable, efficient and well structured. In this work we have compared the SystemVerilog and UVM verification environments. The Inter Integrated Circuit (I2C) Master Core is the Design Under Test (DUT). The environments created using SystemVerilog and UVM, completely wrap the DUT. The assertion coverage found is 100% from both approaches and functional coverage is found as 99.21% and 96.42% from SV environment and UVM environment respectively. Therefore, the overall coverage found is 99.60% and 98.21 from developed SV and UVM environment. Keywords : Environment, I2C, SoC, SystemVerilog, Testbench, Verification, UVM.

DUT Verification Through an Efficient and Reusable Environment with Optimum Assertion and Functional Coverage in SystemVerilog

Verification is the most integral part of chip manufacturing and testing and is as important as the designing. Verification provides with the actual implementation and functionality of a Design under Test (DUT) and checks if it meets the specifications or not. In this paper, a communication protocol has been verified as per the design specifications. The environment so created completely wraps the design under verification and observes an optimum functional and assertion based coverage. The coverage so obtained is 100% assertion based coverage and 83.3% functional coverage using SV (SystemVerilog). The total coverage so obtained is 91.66%.

Design & Assertion Based Verification of Avalon Interrupt Interface

The complexity of ASIC design has increased at an enormous rate in the last few years. This gives rise to difficulties in verification as well. Assertion Based Verification (ABV) provides a solution to this problem. Assertions are used to capture specifications and design intent in an executable form. They help in detecting the bugs faster and closer to the source. In addition to this ABV has a number of advantages such as, detection of corner cases, help in documentation and provide improved design reuse. With the introduction of many standard languages to capture assertions the ABV methodology has gained a lot of popularity. In addition to this many of the simulation tools available today also provide assertion coverage. In this project Avalon Interrupt Interface was designed and verified using assertions. The project carried out involved six stages: RTL design, linting, behavioral simulation, synthesis, Gate Level Simulation (GLS) and adding of assertions. In this project, an RTL design for Avalon Interrupt Interface was developed in VHDL. Testbench was written in Verliog. The design is verified using Accellera PSL assertions along with the test bench. The results were simulated using Aldec Riviera-PRO 2011.02 simulation tool.

Accelerating Assertion Coverage With Adaptive Testbenches

We present a new approach to bias random test generation for accelerating assertion coverage. The novelty of the proposed approach is that it treats the design under test as a black box and attempts to steer the simulation toward coverage points that are relevant for targeted assertions purely through external control. We present this approach over three different models with varying degrees of observability and control. The results demonstrate a significant speedup in assertion coverage as compared to randomized simulation.

Hybrid, Incremental Assertion-Based Verification for TLM Design Flows

Transaction-level modeling is an emerging design practice for overcoming increasing design complexity. This article proposes a methodology for verifying the correctness of RTL refinement from transaction-level modeling. The authors demonstrate the effectiveness of this methodology, guided by an assertion coverage metric on the modules of an industry design.