Abstract
This paper mainly deals with the study of Serial Peripheral Interface and logical Implementation through RTL, Synthesis and Simulation by making Test benches of various modules involved using Universal Verification Methodology. It is done with the help of Questasim 10.0b software. Further, output in both Batch and GUI Mode has been observed and discussed. Various test cases of SPI Protocol are taken into consideration, functional coverage, code coverage, and assertion coverage has been verified by synthesis of various blocks involved in top level architecture of SPI.
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