Design & Assertion Based Verification of Avalon Interrupt Interface

Abstract

The complexity of ASIC design has increased at an enormous rate in the last few years. This gives rise to difficulties in verification as well. Assertion Based Verification (ABV) provides a solution to this problem. Assertions are used to capture specifications and design intent in an executable form. They help in detecting the bugs faster and closer to the source. In addition to this ABV has a number of advantages such as, detection of corner cases, help in documentation and provide improved design reuse. With the introduction of many standard languages to capture assertions the ABV methodology has gained a lot of popularity. In addition to this many of the simulation tools available today also provide assertion coverage. In this project Avalon Interrupt Interface was designed and verified using assertions. The project carried out involved six stages: RTL design, linting, behavioral simulation, synthesis, Gate Level Simulation (GLS) and adding of assertions. In this project, an RTL design for Avalon Interrupt Interface was developed in VHDL. Testbench was written in Verliog. The design is verified using Accellera PSL assertions along with the test bench. The results were simulated using Aldec Riviera-PRO 2011.02 simulation tool.