Aspect Ratio Through Silicon Via Research Articles

Thermal-Mechanical Property of High Aspect Ratio TSV in Advanced IC integration and Packaging

Advanced packaging of integrated circuits (IC) plays a critical role on the way towards high performance, high density, low power consumption and light weight of electronics. Through-silicon vias (TSV) is the heart of 3D IC integration and packaging. However, copper protrusion due to mismatch of coefficients of thermal expansion (CTE) between copper and silicon, which may result in the dielectric material breakdown, becomes the bottleneck of TSV in high-temperature application. In this paper, thermal-mechanical property of high aspect ratio TSV is investigated through experiments under different annealing process, which will help to accelerate the widely application of TSV in advanced packaging of electronics in the future.

Study on the 12 in. wafer uniformity of high aspect ratio TSV filling by using rotation cathode

In 2.5/3D(2.5/3-dimensional) packages, TSV (Through-Silicon Via) technology is crucial for achieving high performance and low power consumption. However, there are still challenges when it comes to uniformly filling TSVs on 300 mm whole wafers without defects. This study focuses on addressing this issue by designing a rotating cathode carrier with a 300 mm diameter, simulating the plating environment in different areas of a 300 mm wafer. The effects of plating conditions, such as cathode rotational speed and chip mounting position, on the filling of TSV are investigated. The TSV have a hole diameter of 10 μm and a depth of 100 μm.The findings reveal that when the cathode carrier rotates at a speed of 30 rpm, different areas of the analog wafer exhibit complete filling of TSV. Additionally, a surface plating layer with an average thickness of approximately 3 μm is obtained.

A Novel 2D/3D X-ray Microscopy Alignment and Inspection Solution for Thermocompression Bonding (TCB) in a Highly Integrated Flip Chip Fan-Out Wafer Level Package (FO-WLP)

As packaging drives to extend the capabilities of Moore’s Law via heterogenous integration, numerous bonding technologies have emerged as potential pathways, allowing for integration of both a variety of devices in the lateral space as well as vertical integration of chips via stacking. As vertical integration on interposer becomes more complex due to shrinking CDs and increasing die layers, alignment and shape control in the bonding process becomes critical. Thermocompression bonding (TCB) is particularly well-suited for larger die, where localized reflow allows a better control of chip gap height and tilt throughout the bonding process. TCB systems require both high accuracy and repeatability in all dimensions to provide a reliable system in package. While a 2D system can provide a plan view assessment of a single bond layer between two chips, it falls short in characterizing the critical z-dimension in a highly integrated chip stacking scenario. Therefore a robust solution is needed for both system alignment validation in the x,y plane as well as a capability to explore gap height and bump quality/buried issues in high aspect ratio TSV. This paper will explore an x-ray application of a stacked 15-layer die-to-interposer structure to qualitatively validate overall health of the TSV (bond, pad, fill) via a nondestructive volumetric method as well as quantitatively evaluate stacked die for via/ball/pad alignment to determine overall alignment shift during the bonding process. In the test vehicle for a flip chip FO-WLP process flow first presented by IMEC, a silicon (Si) bridge is utilized to connect the logic and through-package via dies with a bump pitch of 20µm for the logic die interconnect. This is done by carefully aligning the logic dies on the carrier and then placing the through-package dies aligned to the carrier and logic dies. In the final step, a high accuracy placement and stacking TCB tool attaches the Si bridge. To perform an accurate assessment for bump alignment and bond quality, an initial high-resolution 3D x-ray scan is performed on a 1.5mm3 region of interest with over 2,000 individual projections at a 1.4µm voxel resolution with a 4x objective, taking approximately two hours. The dataset is put through a deep-learning algorithm which generates an AI model. This model is then applied to a faster scan of 15 minutes with a 1.4µm voxel resolution for the same field of view (FOV) on a nearby array and the data is collected and processed. To verify alignment of the entire sample, data is collected on the tightest pitch (in this case 20µm) oriented in both the vertical (x) and horizontal (y) plane in the through-silicon via (TSV) region. The z-plane is analyzed and processed by computer vision algorithms, and individual interconnects are then quantified and sorted for solder height (z), width (x,y) and TSV misalignment (deviation from expected center, x1y1 → x2y2). To validate the model, a high-resolution uncorrected 20h scan and a 15min scan based on deep learning are collected for the same region of interest (ROI). The data is comparable. Furthermore, the global misalignment data between both datasets demonstrates similar misalignment propagating through the 15-layer stack.

Superconformal Film Growth: From Smoothing Surfaces to Interconnect Technology.

ConspectusElectronics manufacturing involves Cu electrodeposition to form 3D circuitry of arbitrary complexity. This ranges from nanometer-wide interconnects between individual transistors to increasingly large multilevel intermediate and global scale on-chip wiring. At larger scale, similar technology is used to form micrometer-sized high aspect ratio through-silicon vias (TSV) that facilitate chip stacking and multilevel printed circuit board (PCB) metallization. Common to all of these applications is void-free Cu filling of lithographically defined trenches and vias. While line-of-sight physical vapor deposition processes cannot accomplish this feat, the combination of surfactants and electrochemical or chemical vapor deposition enables preferential metal deposition within recessed surface features known as superfilling. The same superconformal film growth processes account for the long-reported but poorly understood smoothing and brightening action provided by certain electroplating additives. Prototypical surfactant additives for superconformal Cu deposition from acid-based CuSO4 electrolytes include a combination of halide, polyether suppressor, sulfonate-terminated disulfide, and/or thiol accelerator and possibly a N-bearing cationic leveler. Many competitive and coadsorption dynamics underlie functional operation of the additives. Upon immersion, Cu surfaces are rapidly covered by a saturated halide layer that makes the interface more hydrophobic, thereby supporting the formation of a polyether suppressor layer. Also, halide serves as a cosurfactant supporting the adsorption of amphiphilic molecular disulfide species on the surface while inhibiting copper sulfide formation and incorporation into the growing deposit. Furthermore, the dangling hydrophilic sulfonate end group of the accelerator enables activated metal deposition by hindering polyether suppressor assembly. A common thread in superconformal feature filling is additive-derived positive feedback of the metal deposition reaction within recessed or re-entrant regions. For submicrometer features or optically rough surfaces, area reduction that accompanies the motion of concave surface segments results in the most strongly bound adsorbates' enrichment, which for the suppressor-accelerator systems is the sulfonate-terminated disulfide accelerator species. The superfilling and smoothing process is quantitatively captured by the curvature-enhanced adsorbate coverage mechanism. For larger features, such as TSV, whose depths approach the thickness of the hydrodynamic boundary layer, significant compositional and electrical gradients couple with the metal deposition process to give a negative differential resistance and related nonlinear effects on morphological evolution. For certain suppressor-only electrolytes, remarkable bottom-up feature filling occurs where metal deposition disrupts inhibiting adsorbates at the bottom of the TSV or overruns the ability of the suppressor to form due to kinetic or transport limitations. Because the electrical response to changes in interface chemistry is more rapid than mass transport processes, deposition on planar substrates proceeds by bifurcation into passive and active zones, generating Turing patterns. On patterned substrates, active zone development is biased toward the most recessed regions. The distinction between packaging and on-chip metallization will be blurred as the dimensions of the former merge with those of early day on-chip 3D metallization.

Fabrication and Electrical Characterization of High Aspect Ratio Through-Silicon Vias with Polyimide Liner for 3D Integration.

High aspect ratio (HAR) through-silicon vias (TSVs) are in urgent need to achieve smaller keep-out zones (KOZs) and higher integration density for the miniaturization of high-performance three-dimensional (3D) integration of integrated circuits (IC), micro-electro-mechanical systems (MEMS), and other devices. In this study, HAR TSVs with a diameter of 11 μm and an aspect ratio of 10:1 are successfully fabricated in a low-cost process flow. Conformal polyimide (PI) liners are deposited using a vacuum-assisted spin coating technique, and the effects of spin coating time and speed on the deposition results are discussed. Then, continuous Cu seed layers are fabricated by sequential sputtering and ultrasound-assisted electroless plating. Additionally, void-free and seamless Cu conductors are formed by electroplating. Moreover, a semi-additive method is used to fabricate the redistribution layers (RDLs) on the insulating layers of photosensitive PI (PSPI). Notably, a plasma bombardment process is introduced to remove residual PSPI in the contact windows between RDLs and central pillars. Results show that the resistance of a single TSV from a daisy chain of 144 TSVs with density of 2000/mm2 is about 28 mΩ. Additionally, the S-parameters of a single TSV are obtained using L-2L de-embedding technology, and the experimental and simulated results agree well. The proposed low-cost fabrication technologies and the related electrical characterization of PI-TSVs are significant for the application of HAR TSVs in modern heterogeneous integration systems.

Covalently formation of insulation and barrier layers in high aspect ratio TSVs

Polymers have been widely explored as the alternative material for silicon oxide in through-silicon vias (TSVs). However, an acceptable adhesion between polymers and metallic diffusion barriers is often challenging, especially when it comes to ultrathin films with extremely low roughness. This paper proposes a cost-effective and highly reliable wet deposition path to successively fabricate polyacrylic acid (PAA) insulation films and nickel diffusion barriers on the silicon substrate. PAA films were firstly pretreated to form diazo functional groups through aryldiazonium chemistry. With an electrochemical reduction, catalytic palladium nanoparticles and palladium chelates were introduced to the pretreated substrate by robust Pd-C covalent bonds and electrostatic interaction, respectively. After being immersed into the plating solution, a continuous and uniform nickel layer on the PAA substrate with high adhesion strength can be obtained. Therefore, a stable interface between polymer insulation layers and nickel diffusion barrier can be provided by the proposed covalent fabrication approach. This wet polymer metallization approach on the flat silicon substrate was further extended in TSVs (3 μm × 30 μm) for practical deployment.

Void-free Copper Electrodeposition in High Aspect Ratio, Full Wafer Thickness Through-Silicon Vias with Endpoint Detection

High density interconnects are required for increased input/output for microelectronics applications, incentivizing the development of Cu electrochemical deposition (ECD) processes for high aspect ratio through-silicon vias (TSVs). This work outlines Cu ECD processes for 62.5 μm diameter TSVs, etched into a 625 μm thick silicon substrate, a 10:1 aspect ratio. Cu ECD in high aspect ratio features relies on a delicate balance of electrolyte composition, solution replenishment, and applied voltage. Implementing a CuSO4-H2SO4 electrolyte, which contains suppressor and a low chloride concentration, allows for a tunable relationship between applied voltage and localized deposition in the vias. A stepped potential waveform was applied to move the Cu growth front from the bottom of the via to the top. Sample characterization was performed through mechanical cross-sections and X-ray computed tomography (CT) scans. The CT scans revealed small seam voids in the Cu electrodeposit, and process parameters were tuned accordingly to produce void-free Cu features. During the voltage-controlled experiments, measured current data showed a characteristic current minimum, which was identified as an endpoint detection method for Cu deposition in these vias. We believe this is the first report of this novel endpoint detection method for TSV filling.

Bottom-up Copper Electrodeposition in 20:1 Aspect Ratio, 20 Μm Pitch through Silicon Vias

Heterogeneous integration (HI) offers a path to increase bandwidth density and reducing power consumption per area for advanced microelectronic systems by minimizing fan-in/out structures and reducing parasitics. To achieve state-of-the-art areal bandwidth density, 3D HI is required with through silicon vias (TSVs) with extremely tight interconnect pitches (< 50 µm) and high aspect ratios. Fabrication and fill of these proposed TSVs pose significant challenges including substrate thinning, high aspect ratio deep reactive ion etching (DRIE), conformal thin film deposition to deposit insulating layers as well as seed metals for electrodeposition, and void-free fill of the TSVs. Here, we target an interconnect pitch of 20 µm and TSV diameter of 5 µm. At these dimensions, DRIE lag limits the TSV depth to 100 µm. The TSVs are integrated using a via-last scheme with atomic layer deposition (ALD) Al2O3 as the insulating liner and ALD Pt serving as both the barrier and electrochemical deposition (ECD) seed liner. In this work, we describe the integration scheme for these high density TSVs and focus on the ECD process for achieving a void-free fill with Cu as well as characterization approaches using focus ion beam (FIB) cross sectioning.Recent work on Cu ECD has demonstrated the efficacy of a two-additive acid sulfate electrolyte system based on a chemistry exhibiting a S-shaped negative differential resistance voltammogram1. The electrodeposition system presented is a 1.0 mol/L CuSO4 – 0.5 mol/L H2SO4 acid sulfate electrolyte containing a polyether surfactant and halide additive which promotes a bottom-up Cu growth profile via positive feedback between localized disruption of adsorbed polyether-halide layer and metal deposition. This electrolyte has been applied to potentiostatic filling of a variety of geometries with both micro-scale1 and mm-scale2 TSVs as well as current controlled bottom-up filling from a conformally conductive seed metal3. This system relies on fine tuning of applied bias, adsorbate concentrations, convection, and deposition time to ensure a bottom-up deposition regime is maintained in a particular via geometry.Previous work developed parameters for filling 600 µm deep 5:1 aspect ratio TSVs and the same parameters were applied to 600 µm deep 10:1 aspect ratio TSVs with drastically different filling results.2 In this work, we further adjust the relevant ECD parameters to fill 20:1 aspect ratio TSVs that are 100 µm deep.In fine pitch, high aspect ratio ECD, characterization of the deposited fill profile is important and is difficult to obtain using mechanical cross-sectioning. Here, we use a characterization approach which relies on focused ion beam (FIB) cross-sectioning rather physical grinding and polishing. The FIB mills into the surface of the sample at a 38º angle with respect to the surface of the sample while the electron beam collects a series of images looking down at the sample, as shown in Figure 1.The series of images collected throughout the FIB milling process are then reconstructed to generate a cross-sectional image. FIB cross-sectioning is also used to provide granular detail about deposition morphology and grain size of the ECD Cu that can be lost during mechanical cross-sectioning. Figure 2, shows a top down scanning electron microscopy image of the TSV sample after milling at 38º and the resulting reconstructed cross-sectional image. T. P. Moffat and D. Josell, J. Electrochem. Soc., 159, D208 (2012).L. A. Menk, D. Josell, T. P. Moffat, E. Baca, M. G. Blain, A. Smith, J. Dominguez, J. McClain, P. D. Yeh, and A. E. Hollowell, Journal of the Electrochemical Society, 166 (1) D3066-D3071 (2019).L. A. Menk, E. Baca, M. G. Blain, J. McClain, J. Dominguez, A. Smith, and A. E. Hollowell, Journal of the Electrochemical Society, 166 (1) D3226-D3231 (2019) Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. This work was funded by the DARPA Photonics in the Package for Extreme Scalability (PIPES) program under award number HR001119S0004. The views, opinions, and/or findings expressed are those of the author(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. Figure 1

Copper Electrodeposition in High Aspect Ratio Mesoscale Through-Silicon Vias: Scaling from Die Level to Wafer Level Plating

Three-dimensional (3D) microsystem integration offers solutions for improved device functionality, increased bandwidth per volume, simplified design and assembly, and system miniaturization. Through-silicon vias (TSVs) are a key technology for incorporating devices into 3D integration schemes. Microelectromechanical systems (MEMS) applications often utilize full thickness silicon substrates, creating a need for mesoscale TSVs (> 0.5 mm thick) at high aspect ratios (> 5:1) to facilitate demands of increased interconnect density. Copper (Cu) is a preferred material for TSV filling because of its high electrical and thermal conductivity and can be deposited through electrochemical deposition (ECD) to fill high aspect ratio features. Although Cu ECD has been historically performed using three additive systems, recent work has demonstrated that Cu deposition can be achieved in a simplified CuSO4-H2SO4 electrolyte system with only a single suppressor additive and halide salt.[i],[ii] The cyclic voltammetry (CV) scan for this electrolyte exhibits s-shaped negative differential resistance (S-NDR), observed as hysteresis in the CV voltage-current relationship between forward and reverse scans. Hysteretic voltammetry indicates bifurcating behavior in the electrolyte system, where bottom-up filling is possible in the vias, while the field surface remains passivated. In systems with limited suppression, performing ECD with a sustained potential leads to localized Cu deposition at specific depths within the vias. An increasingly negative potential waveform can be implemented to progressively move deposition vertically through the vias. Achieving a bottom-up, void-free fill with these additive-based electrolytes is typically performed through potentiostatic plating with a reference electrode. Scaling these processes from die level plating experiments, in a small electrochemical cell, to a production-scale full-wafer plating tool requires development of a current-controlled plating regime, because production tools are not equipped with reference electrodes. Furthermore, the developed plating process cannot be highly sensitive to sample rotation rate, because vias at various radial positions across a wafer move at different speeds. In this work, we describe the development of a current-controlled deposition process for bottom-up, void-free filling and further scale this plating process from 1 cm2 sample sizes to a full 150 mm diameter wafer.Voltage-controlled ECD parameters were first established with die level plating experiments. This voltage-controlled process was used to derive a current-controlled ECD procedure, which was followed by sample size scaling experiments and rotation rate studies. The TSV geometries for these experiments had a 10:1 aspect ratio, with via diameters of 62.5 µm, etched into a 625 µm thick silicon substrate. These vias were successfully filled with a potential stepping regime in which the voltage started at -500 mV (MSE) and was gradually incremented to -560 mV (MSE) using -10 mV steps. Time duration at each potential ranged from 2 to 5 hours to achieve a void-free fill. During these voltage-controlled Cu deposition experiments, the resulting current was measured. Subsequent plating experiments were executed by applying current, as opposed to voltage, to mimic the measured current values, and this current-controlled ECD process also achieved void-free filling. Figure 1 shows the development process from voltage-controlled to current-controlled ECD and corresponding mechanical cross sections. As shown in the sample cross sections, these electroplating processes result in fully suppressed deposition on the field area, even though the field is part of the total conducting surface. It was hypothesized that current density scales with via area, as opposed to total conductive surface area; therefore, scaling experiments were performed to understand the relationship between applied current density, total conductive surface area, and active via area. Additionally, with a wafer rotating about its center, solution replenishment within each via is dependent on its radial position. To understand the dependence on solution replenishment and applied bias in a given electrolyte, a series of investigations were performed on samples rotated at different rates. This work presents the results of these studies for establishing a wafer level plating process for 10:1 aspect ratio TSVs. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. SAND2020-5515 C [i] D. Josell and T. P. Moffat, Journal of The Electrochemical Society, 165 (2) D23-D30 (2018). [ii] L. A. Menk, D. Josell, T. P. Moffat, E. Baca, M. G. Blain, A. Smith, J. Dominguez, J. McClain, P. D. Yeh, and A. E. Hollowell, Journal of The Electrochemical Society, 166 (1) D3066-D3071 (2019). Figure 1

Electroless Grafting of Polymer Insulation Layers in Through-Silicon Vias

A through-silicon via (TSV) with a polymeric insulation layer is promising in three-dimensional packaging technology because of its outstanding electrical properties. In this study, we present an electroless grafting method to realize the fabrication of a thin insulation layer in high aspect ratio TSVs. The proposed method is based on the polymerization of a vinyl monomer and an aryl diazonium salt on a silicon surface. Both poly(acrylic acid) and poly(methyl methacrylate) insulation layers were successfully prepared in TSVs to demonstrate the feasibility of the proposed method to fabricate hydrophilic and hydrophobic layers. The resulting polymer insulation layer exhibited high step coverage and superior dielectric properties. The electroless grafting method is a novel synthesis route to prepare polymeric insulation layers with outstanding dielectric properties in high aspect ratio TSVs.

Influence of the Temperature-Dependent Cu+1-Accelerator Complex Formation on Through-Silicon Via Filling

The influence of the temperature-dependent Cu+1-accelerator complex formation on through-silicon via (TSV) filling was studied by means of electrochemical polarization and plating experiments. Electrochemical studies revealed increasing cuprous ion concentration upon addition of the accelerator additive in comparison to the additive-free electrolyte and further increase upon increasing temperature. This indicated formation of a Cu+1-accelerator complex. The electrochemical results were compared to TSV plating experiments at different temperatures. Despite improved mass transport of cupric ions into the high aspect ratio TSV feature at elevated temperatures, large voids were obtained under these conditions, while void-free bottom-up filling was achieved at room temperature. This effect was ascribed to acceleration of the copper deposition in the upper part of the feature due to increasing Cu+1-accelerator complex concentration at higher temperatures. The resulting counter action the effect of the suppressor additive in this part of the features is assumed to yield the observed voids by closure of the features at an early stage of the plating process. Thus, the results presented here reveal the importance of taking into account the comprehensive impact factors on copper deposition for TSV applications and help to improve and fine tune the process to challenging structures.

Pulse Electrodeposition of Cu through-Silicon-Via (TSV) with Surface Suppressor

In recent years, many researches have been focused on the miniaturization of the integrated circuit (IC) feature size to improve the performance of semiconductor devices. However, we are facing the problems such as physical limit of the miniaturization and then increasing processing cost. To overcome these problems the Through-Si-Via (TSV) interconnection, a kind of the 3D interconnection, is a promising technology that could achieve high density, lower energy consumption and high performance in the IC. Since the TSV filling process is costly in the entire TSV process, the TSV filling process which the Cu electrodeposition for TSV is one of key processes. The TSV bottom-up filling which the filling of Cu from the bottom to the top of via with suppressed lateral growth is the solution to ensure a void free filling in high aspect ratio TSV. The bottom-up filling could be achieved by using additives like a suppressor and an accelerator in the electrolyte. In a theoretical model, the suppression breakdown at the bottom of TSV cause the bottom-up filling of TSV. Simultaneous desorption of suppressor by high potential due to ion depletion in the via bottom leads focus of current at the via bottom. Due to adsorption/desorption behavior of the suppressor, the bottom-up TSV filling could be achieved by only using the suppressor.1-3 Furthermore, it was reported that the suppressor at the sidewall is replaced by the accelerator and then the bottom-up filling performance was degraded.3 Lu et al. introduced the nanotwin Cu thin film, which had been attained with pulse electrodeposition.4 Mechanical properties of the Cu thin film is significantly enhanced by highly dense coherent twin boundaries without the degradation of electrical conductivity. Because it could effectively block the dislocation motion without interrupting the migration of electrons.4 The mechanical property of TSV interconnection such as thermal behavior is important as well as the electrical property including electrical conductivity for improvement TSV performance. Therefore, the nanotwin Cu is proper for the TSV interconnection. In this study, nanotwin Cu was applied to fill into high aspect ratio of via (diameter = 5 µm, depth = 60 µm) with pulse current conditions. The deposition condition between direct current and pulse current was compared to observe the filling characteristics. The mechanical properties as the thermal expansion behavior, which is critical to adopting integrated devices, of nanotwin Cu were investigated. As a result, the results with pulse current condition showed obvious improved the TSV filling property than direct current condition. 1. T. P. Moffat and D. Josell, J. Electrochem. Soc., 159, D208 (2012). 2. T. Moffat and D. Josell, Journal of The Electrochemical Society, 159, D208 (2012). 3. L. Yang, A. Radisic, J. Deconinck, and P. M. Vereeckena, J. Electrochem. soc., 160, D3051 (2013). 4. L. Lu, Science, 304, 422-426 (2004).

Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.

Wet Metallization of High Aspect Ratio TSV Using Electrografted Polymer Insulator to Suppress Residual Stress in Silicon

Through-silicon-vias (TSV) are the key to 3-D integrated microsystems. Their fabrication leads to reliability issues linked to the thermo-mechanical stress induced in the silicon around the vias. In this paper, we propose reducing the silicon residual stress in high aspect ratio copper TSVs (HAR TSV) using an electrografted polymer insulator, poly-4-vinylpyridine (P4VP), to replace the traditional silicon oxide layer. We use Raman spectroscopy to make the first investigation of the residual stress in the Si around P4VP-insulated TSVs and compare it to SiO2-insulated TSVs. The results show that P4VP acts as a stress buffer layer because of its particular mechanical properties as the measured residual stress in Si is significantly reduced at room temperature around the polymer insulated HAR TSVs. The potential benefits of such a technology are not only better thermo-mechanical reliability of a 3-D integrated microsystem but also greater integration density.

A Study on the Thermomechanical Reliability Risks of Through-Silicon-Vias in Sensor Applications.

Reliability risks for two different types of through-silicon-vias (TSVs) are discussed in this paper. The first is a partially-filled copper TSV, if which the copper layer covers the side walls and bottom. A polymer is used to fill the rest of the cavity. Stresses in risk sites are studied and ranked for this TSV structure by FEA modeling. Parametric studies for material properties (modulus and thermal expansion) of TSV polymer are performed. The second type is a high aspect ratio TSV filled by polycrystalline silicon (poly Si). Potential risks of the voids in the poly Si due to filling defects are studied. Fracture mechanics methods are utilized to evaluate the risk for two different assembly conditions: package assembled to printed circuit board (PCB) and package assembled to flexible substrate. The effect of board/substrate/die thickness and the size and location of the void are discussed.

Superconformal Bottom-Up Gold Deposition in High Aspect Ratio Through Silicon Vias

This work presents superconformal, bottom-up Au filling of high aspect ratio through silicon vias (TSVs) along with a predictive framework based on the coupling of suppression breakdown and surface topography. The work extends a previous study of superconformal Au deposition in lower aspect ratio TSVs. Deposition was performed in a Na3Au(SO3)2 electrolyte containing a branched polyethyleneimine (PEI) deposition-rate suppressing additive. Voltammetric measurements using a rotating disk electrode (RDE) were used to assess the impact of the PEI suppressor concentration and transport on the rate of metal deposition, enabling the interplay between metal deposition and suppressor adsorption to be quantified. The positive feedback associated with suppression breakdown gives rise to an S-shaped negative differential resistance (S-NDR). The derived kinetics for suppressor adsorption and consumption were used in a mass conservation model to account for bottom-up filling of patterned features. Predictions, including the impact of deposition potential and additive concentration on feature filling, are shown to match experimental results for filling of TSVs. This further generalizes the utility of the additive derived S-NDR model as a predictive formalism for identifying additives capable of generating localized, void-free filling of TSVs by electrodeposition.

Preventing TSV Protrusion Via Controlling Impurity Content in Copper Electrodeposits

3D IC integration is the latest technological breakthrough for maximizing its performance while reducing wiring lengths, interconnection latency, and power consumption. Through-silicon via (TSV) is an essential feature of the 3D IC integration. Filling high aspect ratio TSVs by the conductive materials can be a challenging task. Copper electrodepostion is often adopted due to its optimal electrical preoperties, simplicity, and cost-effectiveness. However, the coefficient of thermal expansion (CTE) of copper is much higher (16.7 ppm/℃) than that of silicon (2.3 ppm/℃). Therefore, the CTE mismatch between copper and silicon substrate can induce thermal stresses, which may lead to TSV protrusion and interfacial delamination. In previous studies, this is mostly managed via suitable heat treatment. This study however proposes a novel method for controlling TSV protrusion. Copper with JGB (Janus Green B, C30H31ClN6) concentration increases (and at the level of 0.2mM of JGB), while the sheet resistance decrease by 7% for the initial resistance. Here, the crystal growth is not observed that is due to impurity pinning or solute dragging effect at grain boundaries. This leads to the conclusion that controlling impurity contents may relieve stress of TSV overhang area. To prevent TSV protrusion, we also perform the same concentration split tests on TSV pattern wafers. Figure 1. EBSD IPF maps of Cu electrodeposit after annealing at 80 ℃ for 90 min with various JGB concentrations of (a) 0, (b) 0.01, (c) 0.03, (d) 0.1, (e) 0.2 and (f) 1 mM in the Cu plating bath. Figure 1

Electroless Plating of Diffusion Barrier Films on SiO2 and Evaluation of Film Characteristics

For fabrication of through-silicon via (TSV) of 3-D integration, sputtering or ALD are used for the barrier and seed layers formation, however, high cost processes using high vacuum instruments have hindered wide application of 3-D integration technologies. We have studied formation of barrier and seed layers with electroless plating which enables significant reduction of fabrication cost [1, 2]. Use of Pd nanoparticle catalyst adsorbed on silane coupling agent at TSV sidewall [3] is very effective for a highly conformal film deposition in the high aspect ratio TSV holes. In this study, we formed electroless barrier films such as CoWP and NiWP on SiO2 at various bath conditions. We evaluated film characteristics such as electrical resistivity, crystalline structure, adhesion property, alloy composition, Cu diffusion barrier properties, etc.Figure 1 shows SEM cross-sectional images of the barrier films and XRD profiles before and after annealing (400 oC, 30min. in vacuum).The crystalline structure of the as deposited CoWP film was amorphous and it remained almost amorphous after heat-treatment. On the other hand, the crystal structure of the as deposited NiWP film was also amorphous, but several peaks of NiP alloy appeared after heat-treatment and it turned to poly crystal film. In addition, we formed Cu seed layer on the barrier metal by displacement plating and studied Cu inter- diffusion properties after annealing. Reference [1] F. Inoue, T. Shimizu, H. Miyake, R. Arima,T. Ito, H.Seki,Y. Shinozaki, T. Yamamoto, and S.Shingubara, Microelectronic Engineering, 106(2013) 164–167. [2] F.Inoue, T.Shimizu, T. Yokoyama, H. Miyake, K. Kondo, T. Saito, T. Hayashi, S. Tanaka, T. Terui and S. Shingubara, Electrochimica Acta, 56-17 ,6245-6250, (2011). [3]W. J. Dressick, C. D. Dukey, J. H. Georger. Jr, G. S. Carabrese, and J. M. Calvert, J Electrochem. Soc., 141 (1) 210 (1994) Figure 1

Microstructural Investigation of Pulse Electroplated Copper Trenches Deposited with Organic Additives

Preferential grain orientation of copper (Cu) vias is speculated to result in a decrease in stresses in elastically anisotropic Cu. On the other hand, highly twinned Cu microstructures are known to increase their electromigration resistance and mechanical properties, without significantly degrading electrical performance [1,2]. Therefore, the optimal manipulation of Cu via microstructure could enable the improvement of the reliability of microelectronic devices. In this study, the “tuning” of the microstructure of Cu trenches were achieved by varying the bath’s chemical composition in different trench aspect ratios. The organic additive system comprising of polyethylene glycol (PEG), bis-(sodium sulfopropyl)-disulfide (SPS), and janus green b (JGB) is commonly used in the electroplating of Cu into trenches and higher aspect ratio through-silicon vias (TSV) for microelectronics [3,4]. In this study, copper was pulse-electrochemically deposited (PED) into 500 nm deep trenches of various widths to evaluate the impact of aspect ratio on the evolution of copper microstructure. Trench aspect ratios of 0.25, 1, 2, and 2.78 were investigated. The organic additive concentrations in the PED bath were also adjusted to examine their influence on the Cu microstructure. By metallurgical sample preparation and the focused ion beam (FIB) technique, the sample cross-sections of the Cu filled trenches were revealed for microstructural analysis using electron backscattering diffraction (EBSD). From the EBSD data, the grain orientation and twin boundary distribution of the deposited Cu microstructure were analyzed.

Electrografted P4VP as Dielectric in High Aspect Ratio TSV: Surface Preparation and Thermomechanical Consideration

A challenge to most 3D integration approaches is the deposition of the Through-Silicon-Via (TSV) dielectric layer. A TSV is traditionally electrically insulated from the silicon substrate by a thin SiO2 film. As TSV aspect ratio gets higher, conformal SiO2 dielectric deposition becomes much more challenging. Alchimer has proposed as dielectric, the use of a highly conformal organic (poly-4-vinylpyridine, P4VP) as dielectric, electrografted through electrochemical reduction of diazonium salts in aqueous media. Surface cleaning prior to electrografting process is a challenge, especially in via last approach. Moreover, the thermomechanical behavior of P4VP coated TSVs remains unknown. This information is most relevant for the layout optimization of 3D integrated microsystems. We will discuss the TSV surface preparation challenge prior to the electrografting process and present the first measurements of the stress induced in the silicon substrate around TSV insulate by P4VP.