Arithmetic Unit Research Articles

A Fast Spiking Neural Network Accelerator based on BP-STDP Algorithm and Weighted Neuron Model

Spiking neural networks (SNNs) are inspired from biological brains and have demonstrated great energy efficiency on hardware computing platforms. However, it is a challenge to implement an online training algorithm on SNN hardware to adapt to the realistic cognitive applications. Besides, the accuracies of SNN adopted rate-based coding scheme are highly depend on the number of coding timesteps, resulting in the long data processing time and massive power consumption. In this brief, a multilayer online training SNN accelerator based on spike-timing-dependent plasticity based back-propagation (BP-STDP) algorithm is carried out. To speed up the spike processing, a weighted neuron model is proposed according to the characteristics of BP-STDP training algorithm. In addition, the training module can reuse the integrate and fire arithmetic unit circuits in hidden layer neuron module, which can significantly reduce the hardware overheads. The proposed accelerator is verified on the Xilinx Virtex-7 FPGA under 100Mhz clock frequency for the application of handwritten digit recognition. The proposed accelerator achieves a 95.3% recognition accuracy rate while consuming 0.27 ms for recognizing one image, and 1.22 ms for training one image. Compared with the software implementation, the proposed accelerator demonstrates <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$41.87\times $ </tex-math></inline-formula> training speedup and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$56.96\times $ </tex-math></inline-formula> recognizing speedup.

Design and Implementation of Arithmetic and Logic Unit (ALU) using Novel Reversible Gates in Quantum Cellular Automata

Design and Implementation of Arithmetic and Logic Unit (ALU) using Novel Reversible Gates in Quantum Cellular Automata

Optimization for deep convolutional neural network of stochastic computing on MLC-PCM-based system

Deep convolutional neural networks (DCNNs) are one of the most promising models for pattern recognition and classification tasks. With the development of wearable devices and the Internet of Things (IoTs), integrating DCNNs onto embedded and portable devices is becoming more and more desirable. However, it is hard to deploy large-scale DCNNs that consume huge power and need many hardware resources in embedded devices with limited power and resources. Previous studies propose that stochastic computing (SC) can replace the resource-consuming binary arithmetic operation in DCNN, which not only simplifies the hardware implementation of arithmetic units but also has the potential to meet the low power requirements of embedded devices. However, bit-streams in SC usually have more bits than the original binary numbers, which inevitably leads to greater storage pressure. To overcome these limitations, in this work, we use Multi-Level Cell (MLC) Phase Change Memory (PCM) which has very low leakage power and high density to replace dynamic random access memory (DRAM) as the weight storage of DCNN. We design SC-PCM, an MLC PCM optimization technology dedicated to SC, which optimizes the write latency and power consumption of MLC PCM. We propose an effective layer-wise multi-precision SC-DCNN model, which reduces the scale of the neural network without sacrificing the accuracy of the DCNNs.

Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations

The main focus of approximate dividers has been on ASIC-based designs. However, for emerging applications, there is a need to design approximate arithmetic units compatible with FPGA applications due to their inherent capabilities. A separate approximate design concept for ASIC and FPGA systems diminish the benefits of approximate computing techniques. This work proposes an energy-efficient and logarithmic-based approximate divider (LEAD), suitable for both ASIC and FPGA-based applications. LEAD is based on functional approximation of arithmetic divider by rounding the inputs to nearest powers of two and computing division using basic addition/subtraction operations and shifters. The proposed approximate design is error-configurable and can be used for both signed and unsigned integers. The results show that the proposed unsigned 16-bit approximate design accomplishes 70% energy-efficiency compared to an accurate array divider on ASIC platforms with minimal accuracy loss. For FPGA implementation, the design shows minimum area utilization and energy savings of around 50% as compared with Vivado divider IPs. A case study in the form of implementation of G.729A voice codec on FPGA and change detection for images is done to illustrate the benefits of the proposed approximate divider design.

QCA with reversible arithmetic and logic unit for nanoelectronics applications

PurposeIn this research work, brief quantum-dot cellular automata (QCA) concepts are discussed through arithmetic and logic units. This work is most useful for nanoelectronic applications, VLSI industry mainly depends on this type of fault-tolerant QCA based arithmetic logic unit (ALU) design. The ALU design is mainly depending on set instructions and rules; these are maintained through low-power ultra-functional tricks only possible with QCA-based reversible arithmetic and logic unit for nanoelectronics. The main objective of this investigation is to design an ultra-low power and ultra-high-speed ALU design with QCA technology. The following QCA method has been implemented through reversible logic.Design/methodology/approachQCA logic is the main and critical condition for realizing NANO-scale design that delivers considerably fast integrate module, effective performable computation and is less energy efficiency at the nano-scale (QCA). Processors need an ALU in order to process and calculate data. Fault-resistant ALU in QCA technology utilizing reverse logic is the primary objective of this study. There are now two sections, i.e. reversible ALU (RAU), logical (LAU) and arithmetical (RAU).FindingsA reversible 2 × 1 multiplexer based on the Fredkin gate (FRG) was developed to allow users to choose between arithmetic and logical operations. QCA full adders are also implemented to improve arithmetic operations' performance. The ALU is built using reversible logic gates that are fault-tolerant.Originality/valueIn contrast to earlier research, the suggested reversible multilayered ALU with reversible QCA operation is imported. The 8- and 16-bit ALU, as well as logical unit functioning, is designed through fewer gates, constant inputs and outputs. This implementation is designed on the Mentor Graphics QCA tool and verifies all functionalities.

Design and simulation of an all-optical 2 × 1 plasmonic multiplexer

Plasmonic devices enable nanophotonics and nanodevices as an alternative to address the miniaturization and diffraction limit problems in photonics devices. An all-optical 2 × 1 multiplexer (MUX) based on aplasmonic multilayer structure (insulator–metal–insulator) is proposed. The working wavelength is 1550 nm and the design area is (350 nm × 250 nm). The proposed device works under the principle of destructive and constructive interference, which happens between inputs and selector signals. The performance of the proposed device is measured by three criteria: transmission, extension ratio, and modulation depth. In transmission signals, an amplifying process occurs; two states are exceeding 100%. The proposed structure dimensions are excellent and optimum according to the value of MD (98.85%). In addition, the operation of the proposed structure is achieved without the need for the control signal, which adds more complicity and degrades the device efficiency. The proposed structure has a major role in building the all-optical arithmetic logic unit, photonics integrated circuits, and THz applications.

Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors

With the rise of edge computing and the advancement of cryptography and error correction codes, portable device processors are demanded to increase their efficiency to run different applications and algorithms. To improve the performance of microprocessors, manufacturers add coprocessors or custom instructions to execute specific operations. Two essential contributions related to the customization of the instruction set are presented in this article. The first is the operator’s improvement for Galoid-field (GF) arithmetic, where the polynomial reduction module is fully programmable using a new zero-padding technique. The second is resource sharing between different operators within the microprocessor. This paper additionally describes two programmable and area-efficient GF arithmetic logic units for soft-core processors. The logic utilization is reduced from 16.67% to 37.00% for the combinational solution and 35.59% to 88.38% for the sequential solution, in ranges from 4 to 64 bits, running on a Kintex-7T field-programmable gate array (FPGA).

Research on Embedded Controller of Hydraulic Vibrating Table Based on DSP

Background: The vibration control loop is the key technology adopt to improve the control performance of the vibration table, which is set outside of the hydraulic vibration table servo control loop. However, the huge number of signal processing work prompts high demands on the calculation ability of the vibration controller. One kind of multi-CPU embedded vibration controller constructed by Digital Signal Processor (DSP) is proposed considering the working principle of the hydraulic vibration table and the Power Spectrum Density (PSD) reproduction process. The embedded controller consists of an acquisition unit, a calculation unit, and a monitoring unit distributes vibration control tasks to the different processing unit to realize distributed algorithm calculations. Every processing unit uses dual-port memory to accomplish data interaction between each other. The development of the embedded controller provides a benchmark engineering case for the design of the hydraulic vibration table vibration controller. Objective: This article focuses on the development of the multi-CPU embedded vibration controller and the distributed calculations. Meanwhile, the power spectrum density experiment is carried out to verify the performance of the hydraulic vibration embedded controller. Methods: 1) The structure of the hydraulic vibration table control system is given, that is, two closed-loop controls. The bandwidth of the system is further broadened by the vibration control of the outer loop. Besides, the accuracy of vibration control is also improved. Then, the development needs of the vibration controller are put forward according to the detailed process of the power spectrum density replication. 2) An arithmetic processing unit is formed by using TI C2000 series DSP to calculate a large number of signal processing and a signal acquisition unit at high speed. In order to improve signal processing efficiency, the signal acquisition unit is used to perform preprocessing calculations (data acquisition and filtering) and vibration control calculations in a distributed manner. 3) Processing speed is further improved by taking full advantage of DSP software sources include lots of library functions and optimized assembly library functions. 4) The friendly operation of the controller and the safety monitoring of the experiment process are realized by the industrial computer served as the human-computer interaction unit. 5) Multi-CPU data sharing is achieved through using dual-port RAM to realize. Results: Through experiments, the developed embedded controller is fully estimated. The experiment shows that the developed hydraulic vibration table can realize real-time vibration control. Concerning the acceleration power spectrum density reproduction experiment, 256 acceleration response samples are calculated, and the update time is 4ms. The tracking accuracy of the timedomain waveform is controlled within 0.3%. Conclusion: The use of the developed embedded controller with signal conditioning equipment can achieve real-time control of the hydraulic vibration table, but the performance of the embedded controller can be promoted in advance, and the performance improvement of the hydraulic vibration table embedded controller can be studied from the following aspects: 1) The Fourier calculation is executed by the acquisition unit to share the calculation workload of the calculation unit; 2) The computing unit uses a signal processor chip with better performance, although this will bring development difficulties; 3) The monitoring computer can use an embedded controller with superior performance instead of an industrial computer to reduce the size, improve the performance; 4) The DSP real-time operating system should be used, and the task scheduling of vibration control experiments should be optimized.

Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic and Antilogarithmic Converter

This brief utilizes the logarithmic number system (LNS) to realize the half-precision division (DIV), square root (SR), and inverse SR (ISR) that are widely used in both the error resilience application and high-performance computing. With the aid of similarities of logarithmic and antilogarithmic functions, the adder tree and multiplexer in the shift-and-add architecture can be shared by the Log and Antilog converter. Moreover, a novel architecture for DIV and SR based on the fused converter is proposed. Compared to the existing works, this new architecture not only achieves a good tradeoff between precision level and hardware efficiency, but also can support more operations (e.g., exponential function, multiplication) with negligible hardware resources. In addition, the proposed architecture can be easily pipelined to further increase the throughput. Furthermore, for some formulas requiring multiple basic operations (e.g., ISR), the advantage of the LNS is more significant.

TAICHI: A Tiled Architecture for In-Memory Computing and Heterogeneous Integration

We present TAICHI, a general in-memory computing deep neural network accelerator design based on RRAM crossbar arrays heterogeneously integrated with local arithmetic units and global co-processors to allow the system to efficiently map different models while maintaining high energy efficiency and throughput. A hierarchical mesh network-on-chip is implemented to facilitate communication among clusters in TAICHI to balance reconfigurability and efficiency. Detailed deployment of the different circuit components is discussed, and the system performance is estimated at several technology nodes. The heterogeneous design also allows the system to accommodate models larger than the on-chip storage capability.

VLSI IMPLEMENTATION OF HIGH SPEED SINGLE PRECESSION FLOATING POINT UNIT USING VERILOG

Single-precision floating-point format is a computer number format that is used to represent a wide dynamic range of values. Floating point numbers representation has widespread dominance over fixed point numbers. Since the recent years, researchers are putting a lot of efforts in interfacing complex modules which are used in signal processing with processors for increasing the speed. In this work implementation of a floating point arithmetic unit which can perform addition, subtraction, multiplication, and division functions on 32-bit operands that use the IEEE 754-2008 standard is done using Verilog. The FPU of this work is a single precision IEEE754 compliant integrated unit. Pre-normalization of operands is employed for addition and subtraction, multiplication using bit pair recoding and division using non restoring division. It can handle not only basic floating point operations like addition, subtraction, multiplication and division but can also handle operations like transcendental functions like sine, cosine and tangential function. The logical method for Addition and Subtraction operation is expanded in order to decrease the no. of gates used.

A stable 4-bit ALU design for printed devices

Printed devices fabricated using roll-to-roll (R2R) printing technology have been used in low-cost Internet of Things (IoTs), smart packaging and bio-chips. As the area of applications of printed devices broadens, arithmetic units in digital design need to be implemented. In this paper, we propose a stable 4-bit arithmetic logic unit (ALU) design using a minimum number of transistors that can overcome the limitations of printed devices. We propose the use of a 2:1 transmission gate (TG) multiplexer structure and hybrid 16T full-adder to construct the ALU. New design methods are applied to reduce the number of inverter stages added to overcome the voltage degradation. Using this approach reduces the total number of transistors used in the design from 276 to 153, compared to the conventional design, with significant improvements in delay and power performance.

POSIT vs. Floating Point in Implementing IIR Notch Filter by Enhancing Radix-4 Modified Booth Multiplier

The increased demand for better accuracy and precision and wider data size has strained current the floating point system and motivated the development of the POSIT system. The POSIT system supports flexible formats and tapered precision and provides equivalent accuracy with fewer bits. This paper examines the POSIT and floating point systems, comparing the performance of 32-bit POSIT and 32-bit floating point systems using IIR notch filter implementation. Given that the bulk of the calculations in the filter are multiplication operations, an Enhanced Radix-4 Modified Booth Multiplier (ERMBM) is implemented to increase the calculation speed and efficiency. ERMBM enhances area, speed, power, and energy compared to the POSIT regular multiplier by 26.80%, 51.97%, 0.54%, and 52.22%, respectively, without affecting the accuracy. Moreover, the Taylor series technique is adopted to implement the division operation along with cosine arithmetic unit for POSIT numbers. After comparing POSIT with floating point, the accuracy of POSIT is 92.31%, which is better than floating point’s accuracy of 23.08%. Moreover, POSIT reduces area by 21.77% while increasing the delay. However, when the ERMBM is utilized instead of the POSIT regular multiplier in implementing the filter, POSIT outperforms floating point in all the performance metrics including area, speed, power, and energy by 35.68%, 20.66%, 31.49%, and 45.64%, respectively.

A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control

This article proposes an automotive safety integrity level (ASIL) D, which is the highest automotive integrity level specified in ISO 26262, and a target application processor for driving automation systems with a high convolutional neural network (CNN) processing performance of 60.4 trillion operations per second (TOPS) with high power efficiency of 13.8 TOPS/W. To achieve both performance and power efficiency, a stream processing architecture specialized for CNN hardware module is adopted to implement many low-power arithmetic units. In addition, 6 MB of local memories are implemented to reduce data transfers between dynamic random access memory (DRAM) and the CNN hardware, thereby improving the execution efficiency of the arithmetic units and saving power consumption caused by the data transfer. In order to support high safety integrity level with power efficiency, we provide safety mechanisms with high failure detection rates only for the hardware used in applications that require ASIL D support. The configuration of two CNN modules can switch between lockstep and single operation depending on the use case, thus achieving a tradeoff between performance and ASIL while maintaining power efficiency. In addition, the freedom from interference (FFI) concept defined in ISO 26262 is achieved by providing mechanisms to prevent low safety level tasks from interfering with high safety level tasks running concurrently inside the processor.

Runtime accuracy alterable approximate floatingpoint multipliers

Modern systems demand high computational power within limited resources. Approximate computing is a promising approach to design arithmetic units with tight resources for error-tolerant applications such as image and signal processing and computer vision. A floating-point multiplier is one of the arithmetic units with the highest complexity in such applications. Designing a floating-point multiplier based on the approximate computing technique can reduce its complexity as well as increase performance and energy efficiency. However, an unknown error rate for upcoming input data is problematic to design appropriate approximate multipliers. The existing solution is to utilize an error estimator relying on statistical analysis. In this paper, we propose new approximate floating-point multipliers based on an accumulator and reconfigurable adders with an error estimator. Unlike previous designs, our proposed designs are able to change the levels of accuracy at runtime. Thus, we can make errors distributed more evenly. In contrast to other designs, our proposed design can maximize the performance gain since reconfigurable multipliers are able to operate two multiplications in parallel once the low accuracy mode is selected. Furthermore, we apply a simple rounding technique to approximate floating-point multipliers for additional improvement. Our simulation results reveal that our new method can reduce area by 70.98% when error tolerance margin of our target application is 5%, and when its error tolerance margin is 3%, our rounding enhanced simple adders-based approximate multiplier can save area by 65.9%, and our reconfigurable adder-based approximate multiplier with rounding can save the average delay and energy by 54.95% and 46.67% respectively compared to an exact multiplier.

Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Arithmetic and logical unit (ALU) are the core operational programmable logic block in microprocessors, microcontrollers, and real‐time‐integrated circuits. The conventional ALUs were developed using complementary metal oxide semiconductor (CMOS) technology, which resulted in excessive power consumptions, path delays, and number of transistors. Therefore, this article focuses on the design and development of hybrid delay‐controlled reconfigurable ALU (DCR‐ALU) using field‐effect transistor (FinFET) and graphene nanoribbon field‐effect transistor (GnrFET) technologies. Initially, a novel carry output predictable full adder (COPFA) and carry input selectable full adders (CISFA) are developed using multiplexer selection logic; then, delay‐controlled hybrid adder (DCHA) and delay‐controlled hybrid subtractor (DCHS) are developed using these full adders. In addition, a unified delay‐controlled hybrid adder and subtractor (DCHAS) is developed by combining these DCHA and DCHS. Further, a delay controller array multiplier (DCAM) also developed using DCHA modules. Finally, DCR‐ALU is developed by adopting the DCHAS, DCAM, and logical operations. The obtained simulation results shows that the proposed nanotechnology‐based models outperformed the conventional adders and subtractors in terms of area, power, and delay reduction.

A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator

The secure hash algorithm 2 (SHA-2) family, including the SHA-224/256/384/512 hash functions, is widely adopted in many modern domains, ranging from Internet of Things devices to cryptocurrency. SHA-2 functions are often implemented on hardware to optimize performance and power. In addition to the high-performance and low-cost requirements, the hardware for SHA-2 must be highly flexible for many applications. This paper proposes an SHA-2 hardware architecture named the multimode SHA-2 accelerator (MSA), which has high performance and flexibility at the system-on-chip level. To achieve high performance and flexibility, our accelerator applies three optimal techniques. First, a multimode processing element architecture is proposed to enable the accelerator to compute various SHA-2 functions for many applications. Second, a three-stage arithmetic logic unit pipeline architecture is proposed to reduce the critical paths and hardware resources. Finally, nonce generator and nonce validator architectures are proposed to reduce memory access and maximize the performance of the proposed MSA for blockchain mining applications. The MSA accuracy is tested on a real hardware platform (the Xilinx Alveo U280 FPGA). The experimental results on the field programmable gate array (FPGA) prove that the proposed MSA achieves significantly better performance, hardware efficiency, and flexibility than previous works. The evaluation results for energy efficiency show that the proposed MSA achieves up to 38.05 Mhps/W, which is 543.6 and 29 times better than the state-of-the-art Intel i9-10940X CPU and RTX 3090 GPU, respectively.

Magnetic Full Adder Based on Negative Differential Resistance-Enhanced Anomalous Hall Effect

Spintronic logic devices have attracted attention because of the prospect of breaking the von Neumann bottleneck through nonvolatile in-memory computing. Although varieties of spin Boolean logic gates have been proposed, spintronic arithmetic logic units such as adders have not been extensively studied because of the difficulties in application of the cascade method of CMOS-based logic in spintronic devices. We experimentally demonstrated a spintronic full adder based on the anomalous Hall effect and geometrical tuning magnetization switching driven by spin-orbit torque. The anomalous Hall effect of magnetic bits was enhanced by nonlinear elements with N-type negative differential resistance to control the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on/off</small> state of <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s, which determined the write voltage of the memory unit. The magnetizations of the memory bits in the memory unit were switched one by one as write voltage increased because of geometry difference. The order of magnetization switching caused the response of the anomalous Hall voltage of the memory unit to the input configurations to conform with the logic function of the full adder. The computation function of the full adder combined with memory writing was experimentally realized with only seven magnetic bits and two steps. The reduced number of magnetic bits and time steps indicated the efficiency of space and time of our device, which is beneficial for practical applications.

A New Multi-Valued Logic Buffer and Inverter Using MOSFET Based Differential Amplifier

The aim of the reported work is to help design of decenary Multi-Valued Logic (MVL) circuits. This paper reports a work, in which, analog voltage-based circuitry is used to design MVL circuits. In this paper, some analog circuits are reported as elements that can be used in Multi-Valued Logic (MVL) circuitry. This article reported a MOSFET-Based Differential Amplifier (MBDA) as a key element in designing decenary MVL arithmetic unit. Operating voltage range and linearity of the gain are two important characteristics of this element. The operating voltage range for the MBDA is 0V to 5.5V as a output voltage.The achieved linear gain is within the range of 0.1V to 5.3V. Analog inverter and correction buffer circuits are reported based on MBDA. Analog inverter will be used in computational and logical decenary MVL circuits. The correction buffer is designed as an element to eliminate noises and signal drift at the output of the MVL gates and during data transfer.

数値精度削減による高速有限要素解析

In most CAE simulations based on the finite element method, double-precision real numbers have been used. On the other hand, due to overwhelming demand for deep learning, low-precision arithmetic is now being introduced into general-purpose processors. By using low-precision real arithmetic for finite element analyses, we can effectively use the arithmetic unit originally equipped for deep learning and obtain advantages in terms of calculation speed. In this study, we propose a fast finite element analysis assisted by deep learning, where low-precision arithmetic is aggressively used to accelerate calculation speed. In the proposed method, deep learning indicates where to use lower precision computation for calculation speed. Here, for the first try, the effect of low precision numbers on numerical quadrature of finite elements is quantitatively investigated through sample analyses.