Arithmetic Unit Research Articles

Comparative Analysis of High Speed and Area Efficient Full-Adder using CMOS and MGDI Techniques

Extremely quick processing is crucial for very large-scale integrated (VLSI) circuits in the arithmetic logic unit. Complementary metal oxide semiconductor (CMOS) and modified gate diffusion input (MGDI) are beneficial technologies for designing high-speed circuits with better reliability and performance with regard to area and power consumption. This research work provides a comparative performance analysis of a full adder that is implemented with CMOS and MGDI technology. This work aims to develop a CMOS-based full-adder and a MGDI-based full-adder circuit for area-efficient and high-speed applications. First, the analysis and implementation of the XOR and NAND logic gates are designed using CMOS technology and the MGDI technique to create a full-adder design. The comparative analysis of integrated circuits in CMOS and MGDI technologies is primarily determined by the number of transistors and delay time. The full-adder is designed and analyzed using 90 nm technology, with performance characteristics evaluated using Cadence Virtuoso Tools.

High-resolution sub-bottom profiling technology using parametric array and vector hydrophone

This paper reports a new method to achieve high-resolution sub-bottom profiling, providing a scheme for the development of Parametric Array Sub-bottom Profiler (PSBP). The high-resolution sub-bottom profiling system is integrated using parametric transmitting array and vector hydrophone, series signal enhancement and high-resolution signal processing methods are proposed to obtain clear sub-bottom profiles. Based on the parametric array, a small-aperture high directivity beam with low frequency, broadband, and without sidelobes is realized, physically achieved high spatial resolution and temporal resolution. By using the vector hydrophone, a single side frequency doubling beamforming (SSFDB) method is used to significantly suppresses the impact of marine environmental noise and sea surface acoustic scattering, the detection resolution is improved due to the frequency doubling characteristics of SSFDB at the same time. Low order bidirectional differential arithmetic unit (LOBDAU) and coherent accumulator (CA) are combined to enhance the echo signal, and finally the high-resolution layering method (HRLM) based on peak detection gives a clear sub-bottom profile of the sediment. The benefits of the combined acoustic array design scheme and the researched signal processing methods had been experimentally evaluated, a clear sub-bottom profile with a semi buried sunken ship was obtained.

Posit and floating-point based Izhikevich neuron: A Comparison of arithmetic

Reduced precision number formats have become increasingly popular in various fields of computational science, as they offer the potential to enhance energy efficiency, reduce silicon area, and improve processing speed. However, this is often at the expense of introducing arithmetic errors that can impact the accuracy of a system. The optimal balance must be struck, judiciously choosing a number format using as few bits as possible, while minimising accuracy loss.In this study, we examine one such format, posit arithmetic as a replacement for floating-point when conducting spiking neuron simulations, specifically using the Izhikevich neuron model. This model is capable of simulating complex neural firing behaviours, 20 of which were originally identified by Izhikevich and are used in this study. We compare the accuracy, spike count, and spike timing of the two arithmetic systems at different bit-depths against a 64-bit floating-point gold-standard. Additionally, we test a rescaled set of Izhikevich equations to mitigate against arithmetic errors by taking advantage of posit arithmetic’s tapered accuracy.Our findings indicate that there is no difference in performance between 32-bit posit, 32-bit floating-point, and our 64-bit reference for all but one of the tested firing types. However, at 16-bit, both arithmetic systems diverge from the 64-bit reference, albeit in different ways. For example, 16-bit posit demonstrates an 18× improvement in accumulated spike timing error over a 1000ms simulation compared to 16-bit floating-point when simulating regular (tonic) spiking. This finding holds particular importance given the prevalence of this particular firing type in specific regions of the brain. Furthermore, when we rescale the neuron equations, this error is eliminated altogether. Although current Posit Arithmetic Units are no smaller than Floating Point Units of the same bit-width, our results demonstrate that 64-bit floating-point can be replaced with 16-bit posit which could enable significant area savings in future systems.

Design of an Efficient Arithmetic and Logic Unit using Coplanar Reversible Full Adder and Modified Fredkin Gates in Quantum Dots Nanotechnology for Digital Signal Processing

Design of an Efficient Arithmetic and Logic Unit using Coplanar Reversible Full Adder and Modified Fredkin Gates in Quantum Dots Nanotechnology for Digital Signal Processing

Development of a high-performance arithmetic and logic unit for efficient digital signal processing based on reversible logic and quantum dots

Digital Signal Processing (DSP) finds a wide range of applications in various fields, including telecommunications, audio and video processing, biomedical engineering, radar systems, and image processing. Previous DSP designs faced limitations in available processing power and computational resources. Insufficient processing power could result in slower execution times, an inability to handle complex algorithms, or limited capacity to process high-speed or large-scale signals. As the demand for minimal power consumption in DSP circuits continues to grow, reversible logic and quantum-dot cellular automata (QCA) have emerged as promising technologies due to their inherent ability to reduce energy loss. Within this landscape, the arithmetic and logic unit (ALU) plays a vital role in complex circuitry, serving as a key component in digital signal processing applications. However, challenges persist, including high quantum cost and the need to limit the number of cells in the ALU design. To address these challenges, our research aims to develop an efficient ALU by integrating reversible logic and QCA technology. Our focus will be on generating essential components, such as Feynman gates, Fredkin gates, and full adder circuits, which serve as foundational building blocks for reversible logic and QCA designs. These components will be combined to construct a comprehensive ALU capable of performing 20 different operations. Our implementation efforts will be centered around QCADesigner, with a specific emphasis on digital signal processing systems that prioritize energy efficiency and optimal utilization of occupied areas.

Autonomous self-healing supramolecular polymer transistors for skin electronics

Skin-like field-effect transistors are key elements of bio-integrated devices for future user-interactive electronic-skin applications. Despite recent rapid developments in skin-like stretchable transistors, imparting self-healing ability while maintaining necessary electrical performance to these transistors remains a challenge. Herein, we describe a stretchable polymer transistor capable of autonomous self-healing. The active material consists of a blend of an electrically insulating supramolecular polymer with either semiconducting polymers or vapor-deposited metal nanoclusters. A key feature is to employ the same supramolecular self-healing polymer matrix for all active layers, i.e., conductor/semiconductor/dielectric layers, in the skin-like transistor. This provides adhesion and intimate contact between layers, which facilitates effective charge injection and transport under strain after self-healing. Finally, we fabricate skin-like self-healing circuits, including NAND and NOR gates and inverters, both of which are critical components of arithmetic logic units. This work greatly advances practical self-healing skin electronics.

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%).

FinFET-Based Low-Power Improved PDP 4:2 Approximate Compressor Design

In the era of low-power very large-scale integration design, approximate computing is a soaring design paradigm that assures energy-efficient circuit design at the cost of some accuracy. Multiplication is a very important operation of an arithmetic unit and compressor is the inherent part of the multiplier. In this paper, an energy-efficient design of a 4:2 approximate compressor is proposed. The inclusion of the extra leakage control transistors in the logic has led to leakage power reduction, which ultimately reduces the power dissipation in the circuits. The proposed 4:2 compressor is simulated at 10[Formula: see text]nm fin-field effect transistor (FinFET) technology. The proposed compressor has been verified for its functionality and robustness. The proposed design shows a power dissipation of 154.48[Formula: see text]nW and a delay of 9.16[Formula: see text]ps. In comparison to other 4:2 approximate compressors, the proposed compressor shows the least power dissipation, the lowest power delay product (PDP) and the highest robustness. The power dissipation of the proposed compressor is 92.84% less than that of the base compressor. The PDP of the designed compressor is 80.58% less than the minimum PDP among other compressors. The aging analysis for the negative bias temperature instability (NBTI) effect is also checked for the proposed compressor and compared with the existing designs.

An efficient approximate multiplier: Design, error analysis and application

Approximate circuits are extensively considered in error-resilient applications to reduce the design complexity. A multiplier is known as a key arithmetic unit of computational block, and thus improving the performance of the multiplier is significantly important to achieve an effective processor. In this paper, we develop two new inaccurate multipliers using approximate 4:2 compressor. Applying error correction block in the structure of these 8-bit multipliers remarkably increases the accuracy of design. The design performance and error metrics of the multipliers are analyzed. Furthermore, as an image processing application, we consider several benchmark images, and compare the quality metrics of image multiplication of our proposed multipliers to those obtained from different under-test multipliers of the previous studies. The design of multipliers is performed using HSPICE with 14 nm FinFET technology. The results demonstrate that the proposed multipliers provide suitable efficiency in the error analysis when compared to the exact multiplier in image processing application.

Low Power Design of Efficient Wireless Sensor Node

Abstract: The escalating demand for rapid, efficient System on Chip (SoC) designs has intensified the need for low-power solutions, particularly in Wireless Sensor Nodes reliant on battery power. This research centers on leveraging clock gating to curtail dynamic power usage in an 8-bit Arithmetic and Logic Unit (ALU). Employing the Hans-Carlson Adder for addition and a 4x4 approximation multiplier, the ALU processes data from a humidity sensor module. Simulations using Xilinx Vivado reveal a substantial 65–73% reduction in power consumption at higher frequencies. This ALU, adept at minimizing power, emerges as a viable processing element for energy-sensitive sensor node applications, ensuring prolonged operational longevity.

A High-Speed Floating Point Matrix Multiplier Implemented in Reconfigurable Architecture

Matrix multiplication is a fundamental operation in computational applications across various domains. This paper introduces a novel reconfigurable co-processor that enhances the efficiency of matrix multiplication by concurrently executing addition and multiplication operations upon matrix elements of different sizes. The proposed design aims to reduce computation time and improve efficiency for matrix multiplication equations. Experimental evaluations were conducted on matrices of different sizes to demonstrate the effectiveness of the processor. The results reveal substantial improvements in both time and efficiency when compared to traditional approaches. The reconfigurable transformation processor harnesses parallel processing capabilities, enabling the simultaneous execution of addition and multiplication operations by partitioning input matrices into smaller submatrices and performing parallel computations, thus the processor achieves faster results. Additionally, the design incorporates configurable arithmetic units that dynamically adapt to matrix characteristics, further optimizing performance. The experimental evaluations provide evidence of reduction in computation time and improvement in efficiency. present significant benefits over traditional sequential methods. This makes this co-processor ideally fit for domains that require intensive linear algebra computations such as computer vision, machine learning, and signal processing.

MODELO SEMÂNTICO DE OPERAÇÕES ARITMÉTICAS E LÓGICAS PARA HARDWARE VIRTUAL

The objective of this project was to develop a semantic model of arithmetic and logical operations for virtual hardware; this goal was achieved through three main steps: Implement logic gates and arithmetic and logic units in Nand2tetris virtual hardware simulator software; Implement recursive and iterative functions to check the correct functioning of logical and arithmetic operations in the p-code machine virtual machine. In the first stage, implementations of the elementary logic gates were developed in the hardware simulator software Nand2tetris. From these logic gates, combinational circuits and sequential circuits were built as logical and arithmetic unit, Half Adder, Full Adder, 16-bit Addition, 16-bit logical negation, 16-bit logical AND, 16-bit logical OR, among others. The second stage involved experimenting at a high level with arithmetic and logical operations, provided by the virtual machine p-code machine, which was implemented in the C programming language, as addition, subtraction, greater than, less than. In the third stage, having already implemented logical and arithmetic operations, iterative and recursive programs were developed to calculate the nth value of the Fibonacci Sequence and the factorial of any number n.

XVDPU: A High-Performance CNN Accelerator on the Versal Platform Powered by the AI Engine

Today, convolutional neural networks (CNNs) are widely used in computer vision applications. However, the trends of higher accuracy and higher resolution generate larger networks. The requirements of computation or I/O are the key bottlenecks. In this article, we propose XVDPU: the AI Engine (AIE)-based CNN accelerator on Versal chips to meet heavy computation requirements. To resolve the IO bottleneck, we adopt several techniques to improve data reuse and reduce I/O requirements. An arithmetic logic unit is further proposed that can better balance resource utilization, new feature support, and efficiency of the whole system. We have successfully deployed more than 100 CNN models with our accelerator. Our experimental results show that the 96-AIE-core implementation can achieve 1,653 frames per second (FPS) for ResNet50 on VCK190, which is 9.8× faster than the design on ZCU102 running at 168.5 FPS. The 256-AIE-core implementation can further achieve 4,050 FPS. We propose a tilling strategy to achieve feature-map-stationary for high-definition CNN with the accelerator, achieving 3.8× FPS improvement on the residual channel attention network and 3.1× on super-efficient super-resolution. This accelerator can also solve the 3D convolution task in disparity estimation, achieving end-to-end performance of 10.1 FPS with all the optimizations.

Advancing nanoscale computing: Efficient reversible ALU in quantum-dot cellular automata

This paper presents a significant contribution to the field of nanoscale computing by proposing an innovative reversible Arithmetic and Logic Unit (ALU) implemented in Quantum-Dot Cellular Automata (QCA). Reversible logic and QCA technology offer promising alternatives to conventional CMOS technology, addressing the challenges of operating at nanoscale dimensions. The primary objective is to develop a highly efficient ALU capable of performing 26 distinct arithmetic and logical operations. The ALU design is based on a novel reversible full adder-subtractor optimized for minimal quantum cost, which is crucial for energy-efficient quantum computation. The evaluation encompasses various criteria related to reversibility, such as gate count, number of constant inputs, number of garbage outputs, and quantum cost. QCA-specific criteria, including cell count, occupied area, and clock cycles, are also considered. The outcomes of this research contribute to the advancement of cell-efficient nanoscale computing, with implications for quantum computation, emerging technologies, and future integrated circuit design.

Microprocessor Design Using COPRAS Method

Introduction: A microprocessor is a computer and An important part of the structure, Without it, on your computer, Nothing can be done. it is a programmable device, It does some arithmetic on the input and logical operations and the desired output creates. In simple words, Microprocessor is on a chip It is a digital device Instructions from memory. Get them and decode them can run and give results. Fundamentals of Microprocessor. In a microprocessor machine language Take some steps that activate them, to the processor That's what it should do says Microprocessor instruction Three basics when implementing Doing things: Its addition, Subtraction, multiplication, division, and some logic functions Arithmetic and Logic Unit (ALU) makes use of. New Microprocessors are floating point Functions in numbers are doing In microprocessors The data in is from one location Can be moved to another location. It is a Program Counter (PC). Contains the registry, which Based on the value of the system address of the next instruction Stores, the microprocessor from place to place Jumps and makes decisions.Research significance: For microprocessor design, this Description Various semiconductors In device fabrication processes Made using some, Consequently in a chip carrier A drop in binding occurs. This chip carrier is then printed. Solder on the circuit board (PCB). done or in the socket is inserted. New microprocessor or microcontroller unit, To make the process flow logically Some general steps can be followed. These few steps make it even easier for small manageable tasks can be separated. A new microprocessor General steps for designing. A must-have in the new app is the determination of skills. required Data path to handle capabilities Set up. Machine code Instructional Design (ISA) Define. data path Create the necessary logic to control.Methodology: An analysis of the COPRAS method in this complex proportionality assessment (COPRAS) system in 1994 showed that the index values used to assess the Gavaskar, Kalkaska, and sarka introduced at this time increased and decreased. Alternatives: Poor life recycled products market, poor consumer perception of recycled products, poor supplier commitment, the poor success of curbside pickup. Evaluation Option: Finance Team, Engagement / Support, Infrastructure Team, Knowledge Team, Environment Team.Alternative: CISC is Intel 386, Intel 486, Pentium, EPIC is IA-64, DEC Alpha 21164. Evaluation preference: Feature size (micron), Supply voltage (V), Die size (mm2), DRAM bits/chip (m).Results: from the result, it is seen that CISC Intel 386 is got the first rank whereas DEC Alpha 21164 is having the lowest rank.

VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration

VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration

Implementation of 64-Bit RISC Processor Using Vedic Multiplier

Abstract: In this project, 64 bit RISC processor designed with Vedic multiplier design. Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is mux- based full adders for building higher bit adders in an area and speed efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. A 64 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx Vivado 2018.3. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. Vedic Multiplier design is based on “Urdhva Triyakbhyam” which is among the 16 Vedic Sutras and MUX-Based Full Adders The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that savings in power in case of MAC and ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced in MAC and ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 64-bit Vedic processor is developed. This reduces the delay and saves area compared to conventional processor. Hence the improvement in speed of operation, and less area utilization are the key features of designed RISC processor.

Enhancing ASIC chip performance through integrated algorithm optimization

As a crucial arithmetic logic unit, the multiplier plays a significant role in digital signal processing. However, multiplication operations often require a large number of calculations and logic gates, leading to increased circuit complexity and power consumption. To enhance the performance and efficiency of multipliers, this paper presents an optimization analysis based on the Wallace Tree and Booth algorithms. The Wallace Tree algorithm decomposes multiplication operations into multiple stages and employs both separate operations and bit-level parallelism to accelerate multiplication, achieving efficient parallel multiplication computations and reducing both latency and area complexity of multiplication. On the other hand, the Booth algorithm is an optimization method for signed binary multiplication. By introducing the concept of Booth encoding, it transforms signed multiplication into unsigned multiplication, thereby reducing the number of multiplication operations. This paper analyses the application and research progress of the Wallace Tree and Booth algorithms in the field of multiplier optimization to improve computational speed and reduce power consumption of multipliers.

Design a 5-stage pipeline RISC-V CPU and optimise its ALU

The RISC-V instruction set has advanced and expanded significantly in recent years. It is an open instruction set architecture (ISA) based on the concept of Reduced Instruction Set Computing (RISC). This article uses Verilog to design a 5-stage pipeline CPU based on RISC-V architecture in Vivado 2022.2. The CPU can execute 38 instructions and optimises its arithmetic logic unit (ALU) by optimising adders, shifters, and multipliers. Next, write a testbench in the simulation software to verify the functionality of the CPU. RTL diagrams and reports are then generated to verify the design structure and evaluate resource allocation. Finally, the CPU successfully executes the instruction and obtains the correct operation result, and the occupation of LUT resources in the shifter part is reduced. This work serves as an important reference for system-on-chip (SoC) and computer design in general. It not only highlights the potential of the RISC-V architecture but also demonstrates the success of optimisation efforts. This paves the way for more powerful and efficient computing systems.

Arithmetic logic unit based on the metastructure with coherent absorption: erratum.

We present a corrigendum to our Letter [Opt. Lett.48, 5699 (2023)10.1364/OL.505761]. In section 3 of the original supplementary material, the absolute value is incorrectly taken in resolving the Kubo formula for describing the conductivity of graphene. Because this is a mistake with the conductivity of graphene, the coupling of the original structure is broken when the correct result is inserted into the code of the transfer matrix. So, the structure of the arithmetic logic unit (ALU), characteristic frequency point, and phase control have been modified accordingly. However, the ultimate function and the conclusion of this work remain unchanged.