An efficient approximate multiplier: Design, error analysis and application

Abstract

Approximate circuits are extensively considered in error-resilient applications to reduce the design complexity. A multiplier is known as a key arithmetic unit of computational block, and thus improving the performance of the multiplier is significantly important to achieve an effective processor. In this paper, we develop two new inaccurate multipliers using approximate 4:2 compressor. Applying error correction block in the structure of these 8-bit multipliers remarkably increases the accuracy of design. The design performance and error metrics of the multipliers are analyzed. Furthermore, as an image processing application, we consider several benchmark images, and compare the quality metrics of image multiplication of our proposed multipliers to those obtained from different under-test multipliers of the previous studies. The design of multipliers is performed using HSPICE with 14 nm FinFET technology. The results demonstrate that the proposed multipliers provide suitable efficiency in the error analysis when compared to the exact multiplier in image processing application.