An efficient design of low-power and high-speed approximate compressor in FinFET technology

Abstract

Nowadays, computer arithmetic logic units extensively utilize inexact computing to improve performance in nano-electronics. One of the vital computational components in microprocessors and digital signal processors is multiplier. Approximate 4:2 compressor is a key element in an approximate multiplier and the optimal design of the compressor directly guarantees the performance of the multiplier. This paper proposes a new low-power and high-speed approximate 4:2 compressor design which leads to a high-speed multiplier. We have designed an 8-bit Dadda multiplier composed of our new compressor and analyzed the multiplier in terms of the error metrics in comparison with its counterparts. As an image processing application of our multiplier, we compared the quality metrics of the image multiplication for different under-test multipliers obtained from the previous studies considering several benchmark images. The simulations are carried out by HSPICE in 14 nm FinFET Technology and approve the efficiency of our design.