Arithmetic Architecture Research Articles

A New Technology for Reducing Power Consumption in Synchronous Digital Design Using Tri-State Buffer

This research paper deals with design and implementation of low power 8-bit arithmetic logic units. The main part of power consumption is consumed in ALU in any processor. Therefore, reducing power dissipation in ALU should be requiring. The proposed technique disabled one of the main block of ALU using tri-state logic which is not necessary to use, except the required processes. In this work, the suggested design is realized by using ASIC methodologies. In order to implement the arithmetic and logic architectures, 130 nm standard cell libraries are used for ASIC execution. The architecture of the design has been created using Verilog HDL language. In addition, it is simulated using ModelSim-Altera 10.3c (Quartus II 14.1) tools. By using tri-state technique, dynamic power and total power are decreased

DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications.

Mathematical model and implementation of rational processing

Precision in computations is a considerable challenge to adequately addressing many current scientific or engineering problems. The way in which the numbers are represented constitutes the first step to compute them and determines the validity of the results. The aim of this research is to provide a formal framework and a set of computational primitives to address high precision problems of mathematical calculation in engineering and numerical simulation. The main contribution of this research is a mathematical model to build an exact arithmetical unit able to represent without error rational numbers in positional notation system. The functions under consideration are addition and multiplication because they form an algebraic commutative ring which contains a multiplicative inverse for every non-zero element. This paper reviews other specialized arithmetic units based on existing formats to show ways to make high precision computing. It is proposed a formal framework of the whole arithmetic architecture in which the operators are based. Then, the design of the addition operation is detailed and its hardware implementation is described. Finally, extensive evaluation of this operator is performed to prove its ability for exact processing.

Parallelization of scalable elliptic curve cryptosystem processors in GF(2m)

The parallelization of scalable elliptic curve cryptography (ECC) processors (ECPs) is investigated in this paper. The proposed scalable ECPs support all 5 pseudo-random curves or all 5 Koblitz curves recommended by the National Institute of Standards and Technology (NIST) without the need to reconfigure the hardware. The proposed ECPs parallelize the finite field arithmetic unit and the elliptic curve point multiplication (ECPM) algorithm to gain performance improvement. The finite field multiplication is separated such that the reduction step is executed in parallel with the next polynomial multiplication. Subsequently, the finite field arithmetic of the ECPs are further parallelized and the performance can be further improved by over 50%. Since the multiplier blocks consume a low number of hardware resources, the latency reduction outweighs the cost of the extra multiplier resulting in more efficient ECP designs. The technique is applied for both pseudo-random curve and Koblitz curve algorithms. A novel ECPM algorithm is also proposed for Koblitz curves that take advantage of the proposed finite field arithmetic architecture. The implementation results show that the proposed parallelized scalable ECPs have better performance compared to state-of-the-art scalable ECPs that support the same set of elliptic curves.

High Frequency Electromyogram Noise Removal from Electrocardiogram Using FIR Low Pass Filter Based on FPGA

With improvements in capacity and performance and a decrease in cost, FPGAs have become a viable solution for making custom chips and programmable DSP devices. This paper presents an efficient implementation of Finite Impulse Response Filter (FIR) using Distributed Arithmetic (DA) architecture based on FPGA with the help of Xilinx system generator software. Here, the multipliers in FIR filter are replaced with multiplier less DA based technique to remove high frequency Electrocardiogram (EMG) noise from ECG signal. As digital filters plays very significant role in the analysis of the low frequency components in Electrocardiogram (ECG) signal. The ECG is susceptible to noise and it is essential to remove the noise to support decision making for specialist and automatic heart disorder diagnosis systems. We proposed that the signals under experiment has been added with muscle noise and after applying different FIR method, the signals according to signal noise ratio (SNR) and MSE(mean square error) are evaluated. It introduces an effective technique for the denoising of ECG signals corrupted by High frequency muscles contraction noise. The performances of the system were evaluated using the Massachusetts Institute of Technology University and Beth Israel Hospital (MIT-BIH) database. Muscle noise is taken from MIT-BIH noise stress database . Simulation results shows that High frequency EMG noise from ECG was removed effectively by using FIR low pass filter. The implementation is done on a Xilinx chip of Spartan 3E XC3S500e-4fg320 using Xilinx system generator 10.1 with Matlab version7.4.0 (2007a).

Performance Analysis of Reversible Finite Field Arithmetic Architectures Over GF(p) and GF(2m) in Elliptic Curve Cryptography

Elliptic curve cryptosystems (ECC) are becoming more and more popular and are included in many standards, as they offer high security strength when compared with other conventional public-key cryptosystems, for the same key length. But the security strength of hardware implementations of ECC is challenged by side channel attacks (SCA) such as power analysis. Reversible logic circuits ideally consume zero energy, which serves as the motivation to implement cryptographic algorithms against power analysis attacks. This paper proposes two new hardware architectures for performing montgomery multiplication in GF(p) and GF(2m), as they are the power consuming operations in ECC. The two architectures are optimized to reduce the hardware cost and they are then implemented in reversible logic with reduced number of quantum cost. In this work, the reversible logic synthesis is performed with Toffoli family of reversible gates. The performance metrics of all the multipliers are analyzed and properly tabulated. Scalar multiplication on elliptic curve points, which is the core operation used in every elliptic curve cryptosystem, has been implemented in reversible logic by using the proposed reversible montgomery multipliers.

A semi-systolic Montgomery multiplier over <i>GF</i>(2<i><sup>m</sup></i>)

In this study, we present an efficient finite field arithmetic architecture based on systolic array for multiplication which is a core algorithm for division and exponentiation operations. In order to obtain dedicated area-efficient circuits, we adopt Montgomery multiplication algorithm and systolic array. First of all we induce an efficient arithmetic algorithm from typical Montgomery multiplication using an effective factor, then we design an efficient semi-systolic array based multiplication architecture which is highly suitable for pipelined operations. The proposed multiplier saves at least 40% area complexity as compared to the corresponding existing structures.

English

2 ABSTRACT: This paper reports the effect of various dopants on the electronic properties of Zig-Zag (4, 0) semi- conducting single walled two probe Carbon Nanotube system using first principle calculations and Non-Equilibrium Green's Function (NEGF) method. The modeled Zig-Zag (4,0) single walled Carbon Nanotube was doped with atoms of elements Tellurium (Te), Antimony (Sb), Arsenic (As) & Chromium (Cr) using Atomistic Tool Kit (version 13.8.1) software and its graphical interface (custom analyzer) Virtual Nanolab. The simulations were carried out in device mode using Density Function Theory (DFT) calculations. The current-voltage (I-V) characteristics & conductance of the four proposed models were studied for comparative study under low-bias conditions. The results show that Arsenic doping has increased the conductance of the model manifold than other doping atoms whereas Chromium doping has showed an amazing property of Negative Differential Resistance (NDR). Hence, we conclude that the proposed model is suitable for use in various CNT based high speed nanoelectronics applications including amplification, oscillation and arithmetic architectures.

English

In Digital Image Processing Point, Line and Edge detection are performed through software approach. The proposed Architecture performs these operations through hardware approach using Distributed Arithmetic. Distributed arithmetic (DA) has been widely used to implement inner product computations with fixed inputs. Conventional ROM-based DA suffers from large ROM requirements. To reduce the memory requirements, Adder based DA uses pre-defined structure for computation. But both the methods are suitable only if at least one input is constant. This project aims to implement a new Distributed Arithmetic Architecture for point detection, line detection and edge detection in DIP when both the inputs are variable. The new architecture is termed as Multiplexer based Distributed Arithmetic (MUX based DA). The proposed architecture takes the advantage of Multiplexer and DA for inner product computations when both the inputs are variable. In addition it reduces ROM requirement and complexity in constructing Adder based architecture for higher order inputs. Here, the performance of proposed Architecture with ROM based DA, Adder based DA and with multiplier based implementation are compared. The MUX based DA reduces power up to 81% and needs 40% of area as compared with multiplier based implementation.

FPGA Implementation of Fir Filter using Distributed Arithmetic Architecture for DWT

This paper presents an efficient FPGA implementation of Finite Impulse Response Filter for Discrete Wavelet Transform using Distributed Arithmetic architecture. This paper proposes a parallel implementation of FIR filter using Distributed Arithmetic Architecture, Distributed Arithmetic Architecture is a multiplier less architecture which uses LookUp Table, ripple carry adder, shift registers. Distributed Arithmetic has an advantaged of less hardware, fast computation time.

Design Arithmetic Circuits Using Quaternary Logic

Arithmetic circuits play a really important role in each all-purpose and application specific procedure circuits. Multiple Valued Logic (MVL) provides the key good thing about the next density per computer circuit space compared to ancient 2 valued binary logic. Quaternary (Four-valued) logic conjointly offers the good thing about simple interfacing to binary logic as a result of base four (=22) permits for the utilization of straight forward encoding/decoding circuits. The purposeful completeness is well-tried with a collection of basic quaternary cells. The library of cells supported the Supplementary Symmetrical Logic Circuit Structure (SUSLOC) square measure designed, simulated, and accustomed build many quaternary fixed-point arithmetic circuits like adders, multipliers. These SUSLOC circuit cells square measure valid mistreatment SPICE models and also the arithmetic architectures square measure valid mistreatment System Verilog models for purposeful correctness. Quaternary (radix-4) twin quantity secret writing principles square measure applied to optimize power and performance of adder circuits mistreatment common place cmos gate technologies. Index Terms: Multiple-valued logic, Quaternarylogic, Modulo-n addition , subtraction and multiplication, Galois.addition and multiplication.

Design Modulo-4 and Galois Field Adder, Subtractor and Multiplier Using Quaternary Logic

Arithmetic circuits play a very necessary role in every general and application specific procedure circuits. Multiple Valued Logic (MVL)provides the key smart factor concerning future density per circuit area compared to ancient two valued binary logic. Quaternary (Four-valued) logic jointly offers the nice factor concerning easy interfacing to binary logic as a results of base four (=22) permits for the use of easy encoding/decoding circuits. The purposeful completeness is proved with a set of basic quaternary cells. The library of cells supported the Supplementary Symmetrical Logic Circuit Structure (SUSLOC) unit of measurement designed, simulated, and accustomed build several quaternary fixed-point arithmetic circuits like adders, multipliers. These SUSLOC circuit cells unit of measurement valid practice SPICE models and additionally the arithmetic architectures unit of measurement valid practice System Verilog models for purposeful correctness. Quaternary (radix-4) twin amount secret writing principles unit of measurement applied to optimize power and performance of adder circuits practice common place cmos gate technologies.

SDR기반 디지털 위성 트랜스폰더를 위한 가변 표본화율의 재귀 연산 구조

위성 트랜스폰더의 설계에 있어서 위성체의 제한된 전원자원으로 인해 연산 알고리즘의 최소화와 하드웨어 구현에 필요한 연산 및 논리 자원의 최소화가 필수적이다. 아울러 위성의 환경에 따라 다양한 대역폭에 대한 효율적 신호처리가 요구되는데 이러한 조건들은 SDR기반의 디지털 방식 구현에 적합하다. 본 논문에서는 SDR 기반의 위성 트랜스폰더 수신부에서 반송파와 레인징 및 Command 부밴드 신호에 대해 각각의 대역과 데이터율을 가변적으로 선택 할 수 있는 하향 표본화기를 제안하였다. 제안된 하향표본화기는 한 개의 하프밴드 필터로부터 재귀적 연산구조를 통해 다수의 임의의 <TEX>$2^M$</TEX>-하향 표본화된 신호를 얻을 수 있으며, 연산량 및 구현에 따르는 논리자원을 최소화 할 수 있다. 또한 재귀적 연산 하드웨어 구현을 위한 알고리즘과 함께 하향표본화에 따르는 대역평탄도 및 에일리어싱을 분석하고 이를 FPGA 실험을 통하여 동작 및 성능을 입증하였다. Due to the limited power supply resources, it is essential that the minimization of algorithmic operation and the reduction of the hardware logical-resources in the design of the satellite transponder. It is also required that the transponder process the signals of various bandwidth efficiently, that is suitble for the SDR-based implementation. This paper proposes a variable rate down sampler which can provide variable bandwidth and data rate for carrier, ranging and sub-band command signals respectively. The proposed down sampler can provide multiple <TEX>$2^M$</TEX> decimated outputs from a single half band filter with recursive arithmetic architecture, which can minimize the hardware resources as well as the arithmetic operations. The algorithm for hardware implementation as well as the analysis for the passband flatness and aliasing is presented and varified by the FPGA implementation.

A New Low-Power Architecture Design for Distributed Arithmetic Unit in FIR Filter Implementation

In this article, an improved Distributed Arithmetic (DA) architecture is proposed, in which the high power consumed by adder units is relocated in the system to reduce the switching activity and total power needed. We used the concept of Time Domain Activity Duration Function (ADF) in architectural-level modification of target units at dynamic operating conditions. The proposed DA exploits the circuit activity, and the adder units are used in minimum states. The proposed DA is a run-time reconfigurable and lets system change the coefficients of FIR filter dynamically. The design was simulated, and the results were verified via two-phase power calculation method. The power calculations are based on forward synthesis invariant points and backward synthesis oriented activity approach. This method was applied to calculate the power and area of the proposed DA and other well-known counterparts in the literature. In the experimental results on 180 nm CMOS ASIC synthesis, the maximum clock of 100 MHz is achieved. In the 32-tap FIR filter implementation of our proposed DA and best known DA2 in serial DA structure, the switching power and internal power improvements are about 21 % and 10 %, respectively, in approximately equal speed and 5 % area increment.

Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits

Galois field arithmetic is a critical component in communication and security-related hardware, requiring dedicated arithmetic architectures for better performance. In many Galois field applications, such as cryptography, the data-path size in the circuits can be very large. Formal verification of such circuits is beyond the capabilities of contemporary verification techniques. This paper addresses formal verification of combinational arithmetic circuits over Galois fields of the type F2k using a computer-algebra/algebraic-geometry-based approach. The verification problem is formulated as membership testing of a given specification polynomial in a corresponding ideal generated by the circuit constraints. Ideal membership testing requires the computation of a Grobner basis, which is computationally very expensive. To overcome this limitation, we analyze the circuit topology and derive a term order to represent the polynomials. Subsequently, using the theory of Grobner bases over F2k, we show that this term order renders the set of polynomials itself a minimal Grobner basis of this ideal. Consequently, the verification test reduces to a much simpler case of Grobner basis reduction via polynomial division, significantly enhancing verification efficiency. To further improve our approach, we exploit the concepts presented in the F4 algorithm for Grobner basis, and show that the verification test can be formulated as Gaussian elimination on a matrix representation of the problem. Finally, we demonstrate the ability of our approach to verify the correctness of, and detect bugs in, up to 163-bit circuits in F2163-whereas verification utilizing contemporary techniques proves infeasible.

Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog

In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix -2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

Realization of FIR Filter Using Modified Distributed Arithmetic Architecture

Realization of FIR Filter Using Modified Distributed Arithmetic Architecture

A Novel Methodology for Memory Reduction in Distributed Arithmetic Based Discrete Wavelet Transform

Discrete Wavelet Transform (DWT) is widely used in image compression standards such as JPEG 2000. DWT can be implemented on FPGA using parallel Distributed Arithmetic (DA) architecture, which is suitable for low power implementation. However, the size of the memory in DA increases with the number of wavelet coefficients. In this paper, we propose a novel methodology to reduce the size of the Look-Up Tables (LUTs) used in DA for DWT. The table entries are sorted using Burrows-Wheeler Transform (BWT) and then compressed. The compressed table is stored in memory. During DWT/IDWT computation, without reconstructing the entire table we can recover only the required table entry. A comparative study of this methodology among different wavelets is performed. We demonstrate that the method is very effective for reducing the memory of DA architectures. A compression ratio of around 2.3:1 is achieved for the look-up table which stores the inner product of high-pass filter coefficients of Daubechies-4 (Db4) wavelet which is used in JPEG2000.

Arithmetic module-based built-in self test architecture for two-pattern testing

Built-in self test (BIST) techniques use test pattern-generation and response-verification operations, reducing the need for external testing. BIST techniques that use arithmetic modules existing in the circuit (accumulators, counters etc.) to perform the testgeneration and response-verification operations have been proposed in the open literature. Two-pattern tests are exercised to detect complementary metal oxide semiconductor (CMOS) stuck-open faults and to assure correct temporal circuit operation at clock speed (delay fault testing). In this study, a novel, arithmetic module-based BIST architecture for two-pattern testing (ABAS) is presented that exercises arithmetic modules to generate two-pattern tests; the hardware overhead required by the presented scheme, provided the availability of such modules is by far the lowest of all schemes that have been presented for the same purpose in the open literature.

A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band

The wide unlicensed bandwidth of a 60 GHz channel presents an attractive opportunity for high data rate and low power personal area networks (PANs). The use of single-carrier modulation can yield energy-efficient transmitter and receiver implementation, but equalization of the long channel response in non-line-of-sight (NLOS) conditions presents a significant challenge. A digital equalizer for 60 GHz channels has been designed for both line of sight (LOS) and NLOS channel conditions to meet the IEEE WPAN standard. Power consumption is minimized by using a parallelized distributed arithmetic (DA) architecture. A 2 mm × 2 mm test chip in 65nm CMOS implements a 6 tap feedforward and 32 tap feedback equalizer that can be configured to cancel the response of up to 72 symbols, and consumes 5.6 mW at 2 Gb/s throughput. The chip also includes a channel estimator based on a Golay correlator for setting the equalizer coefficients and estimating frequency and timing error.