Design Modulo-4 and Galois Field Adder, Subtractor and Multiplier Using Quaternary Logic

Abstract

Arithmetic circuits play a very necessary role in every general and application specific procedure circuits. Multiple Valued Logic (MVL)provides the key smart factor concerning future density per circuit area compared to ancient two valued binary logic. Quaternary (Four-valued) logic jointly offers the nice factor concerning easy interfacing to binary logic as a results of base four (=22) permits for the use of easy encoding/decoding circuits. The purposeful completeness is proved with a set of basic quaternary cells. The library of cells supported the Supplementary Symmetrical Logic Circuit Structure (SUSLOC) unit of measurement designed, simulated, and accustomed build several quaternary fixed-point arithmetic circuits like adders, multipliers. These SUSLOC circuit cells unit of measurement valid practice SPICE models and additionally the arithmetic architectures unit of measurement valid practice System Verilog models for purposeful correctness. Quaternary (radix-4) twin amount secret writing principles unit of measurement applied to optimize power and performance of adder circuits practice common place cmos gate technologies.