Abstract

This research paper deals with design and implementation of low power 8-bit arithmetic logic units. The main part of power consumption is consumed in ALU in any processor. Therefore, reducing power dissipation in ALU should be requiring. The proposed technique disabled one of the main block of ALU using tri-state logic which is not necessary to use, except the required processes. In this work, the suggested design is realized by using ASIC methodologies. In order to implement the arithmetic and logic architectures, 130 nm standard cell libraries are used for ASIC execution. The architecture of the design has been created using Verilog HDL language. In addition, it is simulated using ModelSim-Altera 10.3c (Quartus II 14.1) tools. By using tri-state technique, dynamic power and total power are decreased

Highlights

  • In modern time, power dissipation is a necessary term for all chip designers

  • Dynamic power and total power consumed are reduced in the circuit

  • An 8 bit ALU is designed and powers optimization are achieved by the help of tri-state logic

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Summary

Introduction

Any design consumes power in two types, first is dynamic power consumption and second static power. The static power due to leakage current while the dynamic power consumption due to internal switching of the capacitance [1]. Clock power consumes the main part of the power wasted in ALU. Dynamic power and total power consumed are reduced in the circuit. Power dissipation is estimated by the factors called dynamic power, short circuit power and leakage power including the parameters that used to estimate total power consumption like frequency, switching activity, supply voltage and capacitor [2]. The main part of power consumption dynamic power is switching power defined as [3]: Pdynamic = α * C * V2f (2). From equation 2; α is the switching activity measured in Mw, C is the capacitor measured in

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