Power Reduction Using Efficient Way of Tri-State Buffer Connection

Abstract

Clock gating is a very important technique for decreasing wasted power in digital design. One of the approaches to obtain dissipated power is an intention by the way of masking the clock pulse that is going to the unused part of the design. In this research, a comparative evaluation of current clock gating techniques on synchronous digital design changed into provided. In the new suggested design, the gated clock technology circuit is a use of tri-state buffer and gated clock. The new submodule was created by the connection of two tri-state logic used as switched to control to the design. The new suggested technique was saving more power and area. The suggested sub-module was achieved by using ASIC design methodologies. In order to implement Huffman modules, the architecture of the proposed module has been generated using Verilog HDL language. In addition, it is proved using Modalism-Altera 10.3c (Quartus II 14.1) tools. By using the tri-state technique, dynamic power and total power are decreased. The suggested technique will decrease the hardware complexity.