Adder Architectures Research Articles

A New Carry Look-Ahead Adder Architecture Optimized for Speed and Energy

We introduce a new carry look-ahead adder (NCLA) architecture that employs non-uniform-size carry look-ahead adder (CLA) modules, in contrast to the conventional CLA (CCLA) architecture, which utilizes uniform-size CLA modules. We adopted two strategies for the implementation of the NCLA. Our novel approach enables improved speed and energy efficiency for the NCLA architecture compared to the CCLA architecture without incurring significant area and power penalties. Various adders were implemented to demonstrate the advantages of NCLA, ranging from the slower ripple carry adder to the widely regarded fastest parallel-prefix adder viz. the Kogge–Stone adder, and their performance metrics were compared. The 32-bit addition was used as an example, with the adders implemented using a semi-custom design method and a 28 nm CMOS standard cell library. Synthesis results show that the NCLA architecture offers substantial improvements in design metrics compared to its high-speed counterparts. Specifically, an NCLA achieved (i) a 14.7% reduction in delay and a 13.4% reduction in energy compared to an optimized CCLA, while occupying slightly more area; (ii) a 42.1% reduction in delay and a 58.3% reduction in energy compared to a conditional sum adder, with an 8% increase in the area; (iii) a 14.7% reduction in delay and a 37.7% reduction in energy compared to an optimized carry select adder, while requiring 37% less area; and (iv) a 20.2% reduction in energy and a 55.4% reduction in area compared to the Kogge–Stone adder.

A comprehensive analysis of ultra low power GNRFET based 20T hybrid full adder for computing applications

In an era where energy efficiency is as important as computational speed, this paper introduces a new full adder circuit design that effectively integrates dynamic power gathering (DPG) power conservation benefits with XOR-XNOR pass-transistor logic (PTL) area and performance efficiencies using graphene nanoribbon field-effect transistors. GNRFETs are useful for digital logic due to their high carrier mobility and tunable bandgap. The paper describes the circuit’s seamless transition full adder response, demonstrating the tri-mode dynamic power gating strategy capacity to reduce static power depletion. The proposed hybrid full adder performs well with 7.76 nW power consumption, 481 ps latency, and 3.73 aJ PDP. This reduces power consumption by 99.9%, delay by 99.0%, and PDP by 99.8% compared to other adders. The effects of temperature, voltage, Noise immunity and Carry Forward Adders integration on power, delay, and PDP are also analysed, proving the design’s robustness. The adaptability of our full adder architecture allows its implementation in more complicated arithmetic and logic units, indicating a scalable and energy-efficient paradigm for future integrated circuits.

High – Speed and Low Area-Efficient VLSI Architecture of Three-Operand Binary Adder

Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and Pseudo Random Bit Generator (PRBG) algorithms and also used in many applications. Carry Save Adder (CS3A) is the widely used technique to perform the three- operand addition. In carry save adder at final stage uses ripple carry adder which will cause large critical path delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson Adder (HCA) can also be used for three-operand addition that significantly reduces the critical path delay with more area complexity. Hence, a new high-speed and area-efficient adder architecture is proposed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area and less delay. The effectiveness of the proposed method is designed using Xilinx ISE 14.7

A low-latency and energy-efficient 4-bit absolute value detector for brain-machine interface applications

This research article aims to develop a 4-bit absolute value detector, balancing speed and power efficiency, with potential applications in Brain-Machine Interface (BMI) systems. The detector outputs a binary signal, indicating whether the absolute value of the input surpasses a predefined threshold. The design integrates two primary modules: an absolute value calculator and a comparator. Initially, the study focuses on enhancing the architecture of a multiplexer-based adder for absolute value calculation and selecting an efficient comparator structure, emphasizing least significant bit comparison. Further, the implementation of logic gates using Complementary Metal-Oxide-Semiconductor (CMOS) technology is elaborated. The research concludes by assessing the minimum delay achievable in the critical path, quantified at 74.22 units, and investigating strategies to minimize energy consumption. This is achieved by adjusting gate dimensions and supply voltage, aiming for a delay 1.5 times the minimum. The energy expenditure of the critical path is extrapolated to estimate the overall circuit consumption. The findings demonstrate that, at 1.5 times the minimal delay, the circuit achieves a maximum energy savings of 62.8% with a supply voltage of 0.815V.

A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

Multipliers are essential components within digital signal processing, arithmetic operations, and various computational tasks, making their design and optimization crucial for improving the efficiency and performance of integrated circuits. Among multiplier architectures, Vedic multipliers stand out due to their inherent efficiency and speed, derived from ancient Indian mathematical principles. This study presents a comprehensive analysis and comparison of 4-bit Vedic multiplier designs utilizing Gate Diffusion Input (GDI), Complementary Metal-Oxide-Semiconductor (CMOS), and Transmission Gate (TG) technologies, utilizing different adder architectures such as Ripple Carry Adder (RCA), and Carry Lookahead Adder (CLA), Carry Skip Adder (CSA). The objective is to explore the performance, area, and power consumption characteristics of these multipliers across different technologies and adder implementations. Each multiplier architecture is meticulously designed and optimized to leverage the unique features of the respective technology while adhering to the principles of Vedic mathematics. The designs are evaluated based on parameters such as transistor count, delay, power dissipation, and area. The results demonstrate the effectiveness of GDI technology in terms of in tems of delay, area, power and PDP when compared with other technologies. The 4-bit Vedic multiplier has been designed using 32 nm technology within Tanner EDA software tools.

Energy Efficient Full Swing GDI Based Adder Architecture for Arithmetic Applications

Energy Efficient Full Swing GDI Based Adder Architecture for Arithmetic Applications

DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS

Arithmetic Logic Unit is the brain of all processors, is composed of an Adder circuit. The main component of multiplier circuits is the adder, which performs subtraction (by 2’s complement arithmetic). Since the most fundamental operation in mathematics is addition, and the adder is the most essential part of the processor, the study of VLSI arithmetic has required many digital VLSI researchers. When designing digital systems employing the VLSI approach, the digital adder plays a major role. Low power VLSI based adder designs perform poorly because of the propagation delay issue. With the aid of the PPA design, an assessment of adders’ availability for low power VLSI designs with minimal propagation delay is conducted. Using these performance measures, this study compares and evaluates the performance of several parallel prefix adders, allowing readers to select the optimum adder architecture for their application Specific Integrated Circuits implementations. The three adder topologies taken into considered in this Article include the Han carlson adder, Brent kung, Kogge stone adders. Xilinx ZYNQ XC7Z020 (7000 series) SoC is used to implement the adders using the Vivado Design Suite 2014 and Verilog.

Area and delay efficient RNS-based FIR filter design using fast multipliers

In today's digital age, speed, and area are the primary design concerns. Increasing the rate at which multiplication and addition are performed has always been a need for developing cutting-edge technologies. Wallace multipliers, and Dadda multipliers, are one of the fastest multipliers used in many processors to accomplish fast arithmetic operations. A novel approach to design a LookUp Table (LUT) multiplier was proposed and implemented in Finite Impulse Response (FIR) filter. To improve the Residue Number System (RNS) based FIR filter's performance, several adders like Carry Look ahead (CLA) adder, Kogge Stone adder (KSA) and proposed adder architectures have been implemented. When compared with the 16 tap with 32 bit proposed adder with LUT multiplier, the hardware resource utilization (Logic Elements) is decreased by 5.97 % and in 32 tap with 16 bit combination, it decreases by 7.60 %.When compared with 32 tap with 4 bit word length, the proposed adder with LUT multiplier in the highlighted combinations, the Fmax is increased by 19.28 % and in 32 tap with 16 bit, it increases by 29.74 %. The Low-pass RNS FIR filter is designed for a cut-off frequency of 50 Hz and generated filter coefficients in MATLAB and implemented to denoising the ECG signal.

Optimized Multiplier Architectures for Enhanced Performance and Efficiency in MAC Units

This paper investigated the performance of Vedic multipliers in a 32-bit Multiplier-Accumulator Unit (MAC) by comparing Urdhva Tiryakbhyam and Nikhilam Sutras with various adder architectures. The goal was to identify the optimal combination of speed and resource efficiency. Urdhva Tiryakbhyam with CLA emerged as the fastest option, achieving a minimal delay of 0.709 ns. However, this came at the cost of higher resource utilization, measured in Logic Look-Up Tables (LUTs). Conversely, Nikhilam implementations generally required fewer LUTs, making them more resource-efficient, but they exhibited slightly slower performance. CLA consistently delivered the best delay for both Vedic multiplier types among the adder architectures. All the explored configurations are viable for practical implementation on Xilinx ISE 14.7. The key takeaway is that the choice between Urdhva Tiryakbhyam and Nikhilam and the specific adder architecture hinges on the application’s priorities.

Difference Adder Graph Algorithm for Reducing LUT Size

The current study introduces an implementation of the Difference Adder Graph Algorithm (DAGA) using Verilog. DAGA, rooted in graph theory and adder circuits, aims to diminish Look Up Tables (LUTs) and power consumption in Field Programmable Gate Arrays (FPGAs). By reducing the number of LUTs required for a specific functionality, DAGA offers a promising alternative for digital circuit optimization. To evaluate its efficacy, the paper contrasts DAGA with the Multiple Constant Multiplication (MCM) method, which leverages Carry Save Adder (CSA) architecture and exploits signed-digit number representations to minimize LUT usage. Experimental findings reveal DAGA's superiority over MCM in both area and power utilization reduction. Implementation details and results indicate a remarkable 49.29% reduction in LUT count and a corresponding 41.8% decrease in power consumption for digital circuits. These outcomes underscore the effectiveness of DAGA in enhancing FPGA efficiency, highlighting its potential as a valuable tool for digital circuit designers seeking to optimize performance and power utilization.

Area Efficient Skyrmion Logic based Approximate Adder Architecture Design Methodology

Area Efficient Skyrmion Logic based Approximate Adder Architecture Design Methodology

Analysis of Parallel Prefix Adders

Abstract: Parallel prefix adders are essential components of contemporary digital arithmetic circuits and are found in many different devices, including digital signal processors and microprocessors. In order to improve the effectiveness and performance of parallel prefix adders, this research investigates their design and optimization. This paper analyses in detail the state of the parallel prefix adder architectures and provide new designs that minimize power consumption and critical path delays. The speed and area efficiency benefits of the parallel prefix designs with thorough simulations and comparisons is reviewed. This research have ramifications for high-performance computing systems and point to interesting avenues to further the state of the art in parallel prefix adder design.

Enhancing Surface Electromyography (sEMG) Signal Processing through a Four-bit Absolute Value Comparator

This paper delves into the realm of Surface Electromyography (sEMG) signal processing, presenting a comprehensive exploration of its theoretical underpinnings and the application of a four-bit absolute value comparator. The journey commences with an introduction to the subject matter, followed by an in-depth analysis of the theoretical basis of sEMG signals, encompassing their definition and waveform characteristics, as well as the processing flow. The focal point of this study is the utilization of a four-bit absolute value comparator in enhancing sEMG signal processing. Moving forward, the paper delves into the intricacies of logic circuit design, elucidating the architecture of both adder and comparator circuits pivotal in this context. Circuit optimization strategies are subsequently unveiled, addressing critical path considerations, gate sizing, and VDD optimization to bolster efficiency. In summation, this research advances our understanding of sEMG signal processing and introduces a novel four-bit absolute value comparator, which holds promise in elevating the precision and reliability of sEMG data analysis.

A Higher radix architecture for quantum carry-lookahead adder

In this paper, we propose an efficient quantum carry-lookahead adder based on the higher radix structure. For the addition of two n-bit numbers, our adder uses O(n)-O(frac{n}{r}) qubits and O(n)+O(frac{n}{r}) T gates to get the correct answer in T-depth O(r)+O(log {frac{n}{r}}), where r is the radix. Quantum carry-lookahead adder has already attracted some attention because of its low T-depth. Our work further reduces the overall cost by introducing a higher radix layer. By analyzing the performance in T-depth, T-count, and qubit count, it is shown that the proposed adder is superior to existing quantum carry-lookahead adders. Even compared to the Draper out-of-place adder which is very compact and efficient, our adder is still better in terms of T-count.

A Monotonic Early Output Asynchronous Full Adder

This article introduces a novel asynchronous full adder that operates in an input–output mode (IOM), displaying both monotonicity and an early output characteristic. In a monotonic asynchronous circuit, the intermediate and primary outputs exhibit similar signal transitions as the primary inputs during data and spacer application. The proposed asynchronous full adder ensures monotonicity for processing data and spacer, utilizing dual-rail encoding for inputs and outputs, and corresponds to return-to-zero (RtZ) and return-to-one (RtO) handshaking. The early output feature of the proposed full adder allows the production of sum and carry outputs based on the adder inputs regardless of the carry input when the spacer is supplied. When utilized in a ripple carry adder (RCA) architecture, the proposed full adder achieves significant reductions in design metrics, such as cycle time, area, and power, compared to existing IOM asynchronous full adders. For a 32-bit RCA implementation using a 28 nm CMOS technology, the proposed full adder outperforms an existing state-of-the-art high-speed asynchronous full adder by reducing the cycle time by 10.4% and the area by 15.8% for RtZ handshaking and reduces the cycle time by 9.8% and the area by 15.8% for RtO handshaking without incurring any power penalty. Further, in terms of the power-cycle time product, which serves as a representative measure of energy, the proposed full adder yields an 11.8% reduction for RtZ handshaking and an 11.2% reduction for RtO handshaking.

A Parallel Prefix Modulo-(2 q + 2 q−1 + 1) Adder via Diminished-1 Representation of Residues

Diminished-1 representation of modulo-(2q+1) residues provides for delay-balanced adders for the popular moduli set τ=2q+2q±1. Besides, conjugacy of moduli 2q±1 leads to efficient multiple-residue to binary conversion. Nevertheless, cardinality of τ does not cover the required dynamic range of some applications that also require small q-values for gaining the desired arithmetic speed (e.g., convolutional neural networks). The recently proposed parallel prefix modulo-(2q+2q-1-1) addition scheme provides for balanced performance with similar adder architectures for the moduli of doubly-wide τ (i.e., τ2q+22q±1). Should there be a compatible adder for the conjugate modulo 2q+2q-1+1, the new moduli set τ+2=22q,22q±1,2q+2q-1±1 can provide more than (8q-3) bits of dynamic range, with equally fast adders as those of τ2, whose dynamic range is only 6q bits. Therefore, we were motivated to propose the new modulo 2q+2q-1+1 and its equally fast parallel prefix adder with compatible cost as of its conjugate modulo. This is actually achieved via diminished-1 representation of residues, where those in 1,2q+2q-1 are encoded as 0,2q+2q-1-1 and a zero indicator bit is set for 0-valued residues. The VLSI simulation and synthesis results, especially for the common cases of q=2p, confirm the analytical evaluations regarding the balanced performance of the conjugate moduli 2q+2q-1±1.

Area & power modeling for different tree topologies of parallel prefix adders

Parallel prefix adder (PPA) being an indispensable component of processors needs prompt estimation of design metrics at the initial stage of design cycle. However, the available commercial tools take significant amount of time for the estimation process. The prior availability of area and power models can greatly reduce time-to-market. Symmetrical construction and quick computational ability of PPAs make them competent candidates for adder circuits in complex applications. This paper proposes area and power models for Field Programmable Gate Arrays (FPGA) implementation of classic PPAs, targeted to Xilinx Zynq-7000 family. The available literature barely presents parameters estimation and their analysis for PPAs. Therefore, modeling proposed in this paper is a novel work. PPA structures are simulated, synthesized and implemented using commercial tool i.e. VIVADO IDE. Models have been developed using curve fitting and validated against commercial tool. Results show an average estimation error ranging from 0.37% to 1.34% in case of area modeling and 0.23% to 0.59% in case of power modeling which are comparable with state of the art.

A Novel High Computing Power Efficient VLSI Architectures of Three Operand Binary Adders

Directly or indirectly adders are the basic elements in almost all digital circuits, three operand adders are the basic building blocks in LCG (Linear congruential generator) based pseudo-random bit generators. Elementary adders are fast, area and power efficient for small bit sizes. Carry save adder computes the addition in O(n) time complexity, due to its ripple carry stage. Parallel prefix adders such as Han-Carlson compute the addition in O(log(n)) time complexity but at the cost of additional circuitry. Hence new high-speed power-efficient adder architecture is proposed which uses four stages to compute the addition, which consumes less power, and the adder delay decreases to O(n/2). Even though it is not much faster than the High-speed Area efficient VLSI architecture of three operand adders (HSAT3), it computes the addition by utilizing less power. The proposed architecture is implemented using Verilog HDL in Xilinx 14.7 design environment and it is evident that this adder architecture is 2 times faster than the carry save adder and 1, 1.5, 1.75 times faster than the hybrid adder structure for 32, 64, 128 bits respectively. Also, power utilization is 1.95 times lesser than HSAT3, 1.94 times lesser than the Han-Carlson adder, and achieves the lowest PDP than the existing three operand techniques.

Design of High-Speed Area-Efficient VLSI Architecture of 32-Bit Three-Operand Binary Adder

Abstract: Adders are one of the most widely used digital components in digital integrated circuit design. With the advances in technology, the design that offers either high speed, low power consumption, less area, or a combination of them is designed. There are various processes performed by the digital circuits among which arithmetic operations are prominent. Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry save adder (CS3A) is the widely used technique to perform the three-operand addition. However, the ripple carry stage in the CS3A leads to a high propagation delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson (HCA) can also be used for three-operand addition, significantly reducing the critical path delay at the cost of additional hardware. Hence, a new high-speed and area-efficient adder architecture is designed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area, low power, and drastically reduces the adder delay. To design a faster computing system with less hardware we require some other architecture. The proposed architecture will reduce the area as well as the delay by replacing the Han-Carlson adder with the Ladner fisher adder in a Highspeed area-efficient three-operand binary adder. The proposed architecture is synthesized with the zynq-7000 library. The proposed architecture reduces the LUT count and delay by 20 and 0.4 nanoseconds respectively. By using these synthesis results, we noted the performance parameters like the number of LUTs and delay. We compared the adders in terms of LUTs (represents area) and delay value

On the modulo 2n+1 addition and subtraction for weighted operands

In this paper, investigation is performed on the design of efficient modulo 2n+1 adders, subtractors and add/subtract units for weighted operands. The existing modulo 2n+1 adder, subtractor architectures are reviewed and compared. A new efficient modulo 2n+1 adder architecture for weighted operands is also presented. The proposed modulo 2n+1 adders and one of the existing most efficient modulo 2n+1 subtractors are combined into a modulo 2n+1 add/subtract unit. The proposed modulo 2n+1 add/subtract units exhibit decreased area and power complexity when compared to existing ones.