Applied Gate Bias Research Articles

Gate Modulation of Threshold Voltage Instability in Multilayer InSe Field Effect Transistors

We report a modulation of threshold voltage instability of back-gated multilayer InSe FETs by gate bias stress. The performance stability of multilayer InSe FETs is affected by gate bias polar, gate bias stress time and gate bias sweep rate under ambient conditions. The on-current increases and threshold voltage shifts to negative gate bias stress direction with negative bias stress applied, which are opposite to that of positive bias stress. The intensity of gate bias stress effect is influenced by applied gate bias time and the sweep rate of gate bias stress. The behavior can be explained by the surface charge trapping model due to the adsorbing/desorbing oxygen and/or water molecules on the InSe surface. This study offers an opportunity to understand gate bias stress modulation of performance instability of back-gated multilayer InSe FETs and provides a clue for designing desirable InSe nanoelectronic and optoelectronic devices.

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

In this paper, a simple structure for short channel junction-less double gate (JLDG) MOSFET is proposed. Further expression for surface potential of JLDG has been derived using 2D Poisson׳s equation. Based on the proposed analytical model for surface potential distribution along channel thickness and channel length is derived. The proposed junction-less MOSFET has no p-n junction as the doping of channel is same to that of Source/Drain region. The analytical model is compared with numerical solution using ATLAS device simulator. The result shows the variation of channel potential with channel length, channel thickness, doping concentration and applied gate bias. Further, in this paper the analog performance and RF figure of merits (FOMs) have been investigated. The purpose of this research is to provide a physical explanation for improved analog and RF performance exhibited by the device. In this paper major FOMs such as trans-conductance (gm), output conductance (gd), early voltage (VEA), intrinsic gain (AV), trans-conductance generation factor (TGF), cut-off frequency (fT), trans-conductance frequency product (TFP), gain frequency product (GFP), gain trans-conductance frequency product (GTFP) are analyzed. The simulation result shows that the JLDG exhibit a higher trans-conductance, higher cut-off frequency and lower drain conductance.

Degradation of Gate Voltage Controlled Multilevel Storage in One Transistor One Resistor Electrochemical Metallization Cell

Multilevel per cell (MLC), achieved by controlling the compliance current during SET operation, is a common approach to realize high-density storage in resistive random access memory (RRAM). In this letter, we investigated the failure mechanism of the MLC storage in one transistor and one resistor structure. By commonly modulating the amplitudes of gate bias to achieve the MLC, we found some unexpected failed SET operations, which caused the shrinkage of the MLC margin. In situ monitoring of the dynamic voltage drops on both transistor and memory cell revealed that there was an abnormal rise of source potential of the transistor, resulting in the increase of threshold voltage of the access transistor. If the applied gate bias was below the increased threshold voltage, the transistor would not program the RRAM cell successfully. Finally, possible improvement approaches to solve this problem are suggested.

(Invited) Conducting Polymer Transistors Making Use of Activated Carbon Gate Electrodes

The characteristics of the gate electrode have significant effects on the behaviour of organic electrochemical transistors (OECTs), which are intensively investigated for applications in the booming field of organic bioelectronics. In this work, high specific surface area activated carbon (AC) was used as gate electrode material in OECTs based on the conducting polymer poly(3,4-ethylenedioxythiophene) (PEDOT) doped with poly(styrene sulfonate) (PSS).1 We found that the high specific capacitance of the AC gate electrodes leads to high drain-source current modulation in OECTs. Cyclic voltammetry studies, where PEDOT:PSS is used as the working electrode (WE) and AC is used as the reference electrode (RE) and counter electrode (CE), show that high double-layer capacitance and absence of Faradaic processes permit the development of stable OECTs where the channel potential is uniquely determined by the applied gate bias. The intrinsic quasi-reference characteristics of AC electrodes make unnecessary the presence of an additional reference electrode to monitor the OECT channel potential. The ease of process of AC electrodes for in plane, flexible device architectures constitutes a step forward in the search of new electrode materials for OECTs to be used in iontronics, printed electronics, bio analytical sensing, and other organic bioelectronic devices.

(Invited) Anti-Ambipolar, Gate-Tunable p-n Heterojunctions

The recent emergence of two-dimensional (2D) materials has enabled the realization of atomically thin heterostructure devices [1]. Of particular interest are heterojunctions based on p-type and n-type semiconductors since these devices possess non-linear, gate-tunable transport characteristics. Here, we demonstrate a gate-tunable p-n heterojunction diode using thin films of semiconducting single-walled carbon nanotubes (s-SWCNTs) and single-layer molybdenum disulfide (SL-MoS2) as p-type and n-type semiconductors, respectively [2]. The vertical stacking of these two direct band gap semiconductors forms a heterojunction with electrical characteristics that can be tuned with an applied gate bias over a wide range of charge transport behavior ranging from insulating to rectifying with forward-to-reverse bias current ratios exceeding 104. The transfer characteristic of this p-n heterojunction shows a unique 'anti-ambipolar' behavior with two off-states at either extreme of the gate voltage range and a current maximum in the middle. The continuous transition from positive to negative transconductance in an anti-ambipolar characteristic enables operation of analog communication circuits with a reduced number of circuit components compared to unipolar transistors. Anti-ambipolarity can be widely generalized to heterojunctions of other materials such as s-SWCNTs and n-type amorphous indium gallium zinc oxide (a-IGZO), ultimately leading to all solution processed p-n heterojunctions at the wafer scale [3]. [1] D. Jariwala, V. K. Sangwan, L. J. Lauhon, T. J. Marks, and M. C. Hersam, "Emerging device applications for semiconducting two-dimensional transition metal dichalcogenides," ACS Nano, 8, 1102 (2014). [2] D. Jariwala, V. K. Sangwan, C.-C. Wu, P. L. Prabhumirashi, M. L. Geier, T. J. Marks, L. J. Lauhon, and M. C. Hersam, "Gate-tunable carbon nanotube-MoS2 heterojunction p-n diode," Proc. Nat. Acad. Sci. USA, 110, 18076 (2013). [3] D. Jariwala, V. K. Sangwan, J.-W. T. Seo, W. Xu, J. Smith, C. H. Kim, L. J. Lauhon, T. J. Marks, and M. C. Hersam, "Large-area, low-voltage, anti-ambipolar heterojunctions from solution-processed semiconductors," submitted, 2014.

Modulation of transport properties of optimally doped La1.85 Sr0.15 CuO4 thin films via electric field modification of the grain boundaries

Modulation of the transport properties of a superconducting La1.85Sr0.15CuO4-based ionic-liquid gated transistor has been achieved. For an applied gate bias Vg ≥ 2 V, the characteristic sheet resistivity vs. temperature (Rs–T) curves exhibit a fully reversible foot feature below the superconducting transition temperature (Tc). In contrast to the behaviour expected from the large charge carrier density of this high-Tc superconductor material, the normal state conductance above Tc also exhibits a large modulation, indicating a larger charge screening length than that predicted from a simple Thomas–Fermi model. We regard these changes as due to electrostatic modification of the charge density at structural imperfections such as grain boundaries present within the sample. Such modification alters the coupling between superconducting domains and dictates the overall Rs–T trend of the gated film. To explain our findings, we employ Mannhart's model of electronic band bending at the grain boundaries and propose that this band bending can be modulated by large electric fields resulting in the observed modulation of the transport properties of the device.

硬 X 線光電子分光による酸化膜の評価

We report the applications of a hard X-ray photoelectron spectroscopy to the characterization of SiO2/Si(001) systems. Large escape depth of high-energy photoelectron enables us to probe buried layers and their interfaces in multilayer structures. Estimation of SiO2 overlayer thicknesses up to 25 nm by angle resolved XPS was possible in SiO2/Si(001) samples. Determination of the thickness profile of a wedged shape SiO2 buried layer was successfully done in Ir (8 nm)/HfO2 (2.2 nm)/thickness graded-SiO2 (0-10 nm)/Si(100). The Si 1s core level showed a SiO2 thickness dependent shift, which was ascribed to fixed charge at the SiO2-Si interface. Energy distribution of interface states at ultrathin thermal oxide/Si(100) interfaces were determined by Si 1s core level shift by applying gate bias in metal-oxide-semiconductor (MOS) structure with 5 nm Au gate electrodes.

Fabrication and measurement of graphene p–n junction with two top gates

A graphene device with two top gates has been fabricated and measured for the first time. The thickness of the gate dielectric is 60 nm. The measurement results indicate that the externally applied gate biases can dope the underneath graphene to either p- or n-type, forming an induced p–n junction. The current–voltage (I–V) curve measurement results also indicate that there is no nonlinear phenomenon in a weakly induced graphene p–n junction. This graphene p–n junction can potentially be used for terahertz wave generation.

Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlOx) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6V and capacitance of 0.47μF/cm2. Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlOx/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2V under an applied gate bias from 4V to −5V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9×1012cm−2. The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (Ids) after programming and erasing remained in their pristine state after 104s and are expected to be retained for more than one year.

Ion-Induced Charge-Collection Transients in p-Channel AlGaSb/InGaSb Heterojunction Field-Effect Transistors

Ion-induced, time-resolved charge-collection measurements for p-channel AlGaSb/InGaSb field-effect transistors are reported for a range of gate and drain bias conditions. The transient response reveals two distinct contributions: a faster initial response (<;1 ns) followed by a slower, >10 ns, relaxation. The slower contribution depends sensitively on the applied gate bias, is suppressed when the gate is made more positive toward depletion, and is identified with an enhanced source-drain current in which more charge is collected than is deposited by the ion. A model consistent with the experimental measurements suggests that the dynamics of the enhancement processes are associated with the trapping and detrapping dynamics of electrons in the AlGaSb barrier materials.

The Dependence of Carrier Distribution on Gate Capacitance of α-IGZO TFTs

The capacitance-voltage (C–V) characteristics of inverted staggered amorphous indium–gallium–zinc-oxide thin film transistors (α-IGZO TFTs) with various dimensions are investigated by physics-based technology computer aided design (TCAD) simulation. For gate bias lower than the threshold voltage of the TFT, the electrons in the channel region are nearly fully depleted. It causes that the total gate capacitance is determined by the overlap region of gate, α-IGZO, and source/drain metals. When the applied gate bias is higher than the threshold voltage, the high electron density channel with density of ~6 × 1017 cm-3 and thickness of ~3-4 nm is observed near the interface of α-IGZO and gate dielectric. It results that the total gate capacitance is dominated by the gate to channel overlap. Quantitative analysis of the carrier distribution and energy band structures are utilized to study the physical mechanism underlying the C–V characteristics of the α-IGZO TFTs.

Field-induced carrier generation in amorphous-InGaZnO4 thin-film transistors

The positive threshold voltage (VTH) shift induced by positive gate bias stress (PBS) in amorphous-indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs) is commonly attributed to carrier trapping mechanism. Here we show that in addition to these trapping mechanisms, the concentration of donors also increases during PBS when the applied gate bias stress voltage VGS_Stress≤30V. In the early stages of the PBS, this increase in donor concentration may manifest itself as a negative VTH shift. In the case of VGS_Stress≥40V, however, the increase is not detectable because electron trapping at the semiconductor/gate-insulator interface is dominant – even in the early stages of the PBS.

Investigation of the total dose response of partially depleted SOI nMOSFETs using TCAD simulation and experiment

We have analyzed total ionizing dose response of partially depleted SOI nMOSFETs fabricated in a 0.13μm commercial technology assisted by TCAD simulation. Using TCAD tools, the ionizing radiation-induced damages in buried oxide and shallow-trench oxide are investigated separately. It is shown that back transistors are radiation tolerant up to 1Mrad (Si) for core nMOSFETs even under the worst case whereas back transistors of I/O devices are 100krad (Si) due to lower doping concentration. In addition, the enhanced total dose degradation with applied gate bias is attributed to more charge trapped in shallow-trench oxide. 2D cross section electrical simulation schematically illustrates the evolution of charge trapping in buried oxide and shallow-trench oxide. It is found and verified that parasitic corner transistor located at the bottom of swallow-trench oxide plays a critical role on the radiation hardness of partially depleted SOI nMOSFETs.

Modeling Carrier Mobility in Nano-MOSFETs in the Presence of Discrete Trapped Charges: Accuracy and Issues

This paper investigates the accuracy and issues of modeling carrier mobility in the channel of a nanoscaled MOSFET in the presence of discrete charges trapped at the channel/oxide interface. By comparing drift-diffusion (DD) and Monte Carlo (MC) simulation results, a quasi-local mobility model accounting for the complex scattering profile associated with a trapped carrier at the center of the channel is firstly derived. The accuracy of this model is evaluated on a test-bed 25-nm MOS transistor at low drain bias condition and for several applied gate biases. The issues in extending this mobility model to high drain biases regime and to the case of randomly positioned trapped charges are then discussed in the second part of this paper. Our findings show that DD simulations can maintain computational efficiency and accuracy at low drain biases, when a proper mobility model is used to describe the impact of discrete trapped charges. On the other hand, more complex corrections, that go beyond the simple mobility modification, are necessary to compensate the different carrier concentrations between DD and MC approaches at high drain biases.

Analysis of transconductance characteristic of AlGaN/GaN HEMTs with graded AlGaN layer

A theoretical study of transconductance characteristics (gm − Vgs profile) of AlGaN/GaN high electron mobility transistors (HEMTs) with a graded AlGaN layer is given in this paper. The calculations were made using a self-consistent solution of the Schrödinger-Poisson equations and an AlGaN/GaN HEMTs numerical device model. Transconductance characteristics of the devices are discussed while the thickness and Al composition of the graded AlGaN layer are optimized. It is found that graded AlGaN layer structure can tailor device’s gm − Vgs profile by improving polar optical phonon mobility and interface roughness mobility. Good agreement is obtained between the theoretical calculations and experimental measurements over the full range of applied gate bias.

Invited Presentation: Carbon Nanotube Heterostructure Devices

Improvements in carbon nanotube (CNT) monodispersity have yielded corresponding enhancements in the performance of electronic, optoelectronic, sensing, and energy technologies [1]. However, in all of these cases, CNTs are just one of many materials that are employed, suggesting that further device improvements can be achieved by focusing on the careful integration of disparate materials with CNTs. In this talk, several examples will be provided where careful attention to materials integration enables unprecedented opportunities for CNT heterostructure devices. For example, the traditional trade-off between on/off ratio and mobility in semiconducting CNT thin-film transistors is overcome by replacing conventional inorganic gate dielectrics with hybrid organic-inorganic self-assembled nanodielectrics, yielding on/off ratios approaching 106 while concurrently achieving mobilities of ~150 cm2/V-s [2,3]. Similarly, the utilization of unconventional gate electrodes (e.g., Ni) allows the threshold voltage of semiconducting CNT thin-film transistors to be shifted, which enables the realization of p-type enhancement-mode devices. By further integrating benzyl viologen with Ni-gated semiconducting CNT thin-film transistors, complementary n-type enhancement-mode devices can also be demonstrated. The integration of enhancement mode p-type and n-type CNT thin-film transistors then allows for CNT CMOS logic gates to be fabricated with sub-nanowatt static power dissipation and full rail-to-rail voltage swing [4]. Finally, p-type semiconducting CNT thin films are integrated with n-type single-layer MoS2 to form p-n heterojunction diodes [5]. The atomically thin nature of single-layer MoS2 implies that an applied gate bias can electrostatically modulate the doping on both sides of the p-n heterojunction concurrently, thereby providing 5 orders of magnitude gate-tunability over the diode rectification ratio in addition to unprecedented anti-ambipolar behavior when operated as a three-terminal device. In addition, since CNTs and single-layer MoS2 are direct band gap semiconductors, the resulting p-n heterojunctions show a strong and ultrafast photoresponse at near-infrared and visible wavelengths. Overall, this work establishes that CNT-based technology can be substantially enhanced and diversified into new areas through precise integration into heterostructure devices.[1] D. Jariwala, V. K. Sangwan, L. J. Lauhon, T. J. Marks, and M. C. Hersam, “Carbon nanomaterials for electronics, optoelectronics, photovoltaics, and sensing,” Chem. Soc. Rev., 42, 2824 (2013).[2] V. K. Sangwan, R. P. Ortiz, J. M. P. Alaboson, J. D. Emery, M. J. Bedzyk, L. J. Lauhon, T. J. Marks, and M. C. Hersam, “Fundamental performance limits of carbon nanotube thin-film transistors achieved using hybrid molecular dielectrics,” ACS Nano, 6, 7480 (2012).[3] K. Everaerts, J. D. Emery, D. Jariwala, H. J. Karmel, V. K. Sangwan, P. L. Prabhumirashi, M. L. Geier, J. J. McMorrow, M. J. Bedzyk, A. Facchetti, M. C. Hersam, and T. J. Marks, “Ambient-processable high-capacitance hafnia-organic self-assembled nanodielectrics,” J. Am. Chem. Soc., 135, 8926 (2013). [4] M. L. Geier, P. L. Prabhumirashi, J. J. McMorrow, W. Xu, J.-W. T. Seo, K. Everaerts, C. H. Kim, T. J. Marks, and M. C. Hersam, “Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control,” Nano Lett., 13, 4810 (2013). [5] D. Jariwala, V. K. Sangwan, C.-C. Wu, P. L. Prabhumirashi, M. L. Geier, T. J. Marks, L. J. Lauhon, and M. C. Hersam, “Gate-tunable carbon nanotube-MoS2 heterojunction p-n diode,” Proc. Nat. Acad. Sci. USA, 110, 18076 (2013).

A Very High Speed, High Resolution Current Comparator Design

This paper, presents an idea for analog current comparison which compares input signal and reference currents with high speed and accuracy. Proposed circuit utilizes amplification properties of common gate configuration, where voltage variations of input current are amplified and a compared output voltage is developed. Cascaded inverter stages are used to generate final CMOS compatible output voltage. Power consumption of circuit can be controlled by the applied gate bias voltage. The comparator is designed and studied at 180nm CMOS process technology for a supply voltage of 3V. Keywords-Current Mode, Comparator, High Speed, High Resolution.

Enhancing photoresponse by synergy of gate and illumination in electric double layer field effect transistors fabricated on n-ZnO

We report that photoresponse of ZnO in ultraviolet (UV) can be enhanced substantially by simultaneously applying a gate bias in an Electric Double Layer Field Effect Transistor configuration fabricated on ZnO as a channel. The effect arises from synergy between UV illumination and applied gate bias, which leads to a substantial enhancement in the device current. We propose that large carrier density created by the illumination and the gate leads to neutralization of some of the oxygen charged vacancies which in turn reduce potential scattering leading to enhanced field effect mobility. This is verified by gate bias controlled Photo Luminescence experiment.

Two Types of On-State Observed in the Operation of a Redox-Based Three-Terminal Device

A redox-based three-terminal device was fabricated using Ta2O5 as the ionic transfer material, and its operation was investigated. We found that application of a negative polarity gate bias, which increases oxygen anions in the channel regions, can make a conductive path between a source electrode and a drain electrode. The insulating state of the pristine device is turned on to a semiconductor state by the application of a negative polarity gate bias. Since turning off to the insulating state could not be achieved, the switching process resembles the soft breakdown of the first turning-on process of oxygen vacancy controlled resistive random access memories, although the polarity of the bias is opposite to that used in the first turning-on process. Further application of a gate bias causes a transition from the semiconductor state to a metal state. Accordingly, there are two types of on-state. It is possible to switch between the semiconductor and metal states.

Control over band structure and tunneling in bilayer graphene induced by velocity engineering

The band structure and transport properties of massive Dirac fermions in bilayer graphene with velocity modulation in space are investigated in the presence of a previously created band gap. It is pointed out that velocity engineering may be considered as a factor to control the band gap of symmetry-broken bilayer graphene. The band gap is direct and independent of velocity value if the velocity modulated in two layers is set up equally. Otherwise, in the case of interlayer asymmetric velocity, not only is the band gap indirect, but also the electron–hole symmetry fails. This band gap is controllable by the ratio of the velocity modulated in the upper layer to the velocity modulated in the lower layer. In more detail, the shift of momentum from the conduction band edge to the valence band edge can be engineered by the gate bias and velocity ratio. A transfer matrix method is also elaborated to calculate the four-band coherent conductance through a velocity barrier possibly subjected to a gate bias. Electronic transport depends on the ratio of velocity modulated inside the barrier to that for surrounding regions. As a result, a quantum version of total internal reflection is observed for thick enough velocity barriers. Moreover, a transport gap originating from the applied gate bias is engineered by modulating the velocities of the carriers in the upper and lower layers.