Gate Modulation of Threshold Voltage Instability in Multilayer InSe Field Effect Transistors

Abstract

We report a modulation of threshold voltage instability of back-gated multilayer InSe FETs by gate bias stress. The performance stability of multilayer InSe FETs is affected by gate bias polar, gate bias stress time and gate bias sweep rate under ambient conditions. The on-current increases and threshold voltage shifts to negative gate bias stress direction with negative bias stress applied, which are opposite to that of positive bias stress. The intensity of gate bias stress effect is influenced by applied gate bias time and the sweep rate of gate bias stress. The behavior can be explained by the surface charge trapping model due to the adsorbing/desorbing oxygen and/or water molecules on the InSe surface. This study offers an opportunity to understand gate bias stress modulation of performance instability of back-gated multilayer InSe FETs and provides a clue for designing desirable InSe nanoelectronic and optoelectronic devices.