Degradation of Gate Voltage Controlled Multilevel Storage in One Transistor One Resistor Electrochemical Metallization Cell

Abstract

Multilevel per cell (MLC), achieved by controlling the compliance current during SET operation, is a common approach to realize high-density storage in resistive random access memory (RRAM). In this letter, we investigated the failure mechanism of the MLC storage in one transistor and one resistor structure. By commonly modulating the amplitudes of gate bias to achieve the MLC, we found some unexpected failed SET operations, which caused the shrinkage of the MLC margin. In situ monitoring of the dynamic voltage drops on both transistor and memory cell revealed that there was an abnormal rise of source potential of the transistor, resulting in the increase of threshold voltage of the access transistor. If the applied gate bias was below the increased threshold voltage, the transistor would not program the RRAM cell successfully. Finally, possible improvement approaches to solve this problem are suggested.