Analog Circuit Applications Research Articles

Performance Evaluation of 32-nm CNT-OPAMPs in Analog Circuits: Design and Comparison of Leapfrog Filters

In this paper, we have presented the design and characteristic performance evaluation of a 6-order Leapfrog Filter. First we designed the filter by using Silicon-based CMOS Operational Amplifiers (Si-OPAMPs). Then we designed the filter with Carbon Nanotube-based Operational Amplifiers (CNT-OPAMPs) using a benchmark nine-transistor Operational Amplifier (OPAMP) model with single-walled Carbon Nanotube Field-Effect Transistors (SW-CNTFETs) as primary building-blocks for 32nm technology. We compared the performance between the two and achieved higher phase margin, improved power dissipation, and significantly higher input resistance for the CNT-OPAMP based filter. Then we further evaluated the performance of the CNT-OPAMP based filter by changing the number of SWNTs used in the intrinsic channel region of the CNTFET, keeping all other design parameters the same. Our simulation-based assessment has shown a satisfactory superiority for CNT-OPAMP filter design in comparison with Si-based CMOS filter design. The results obtained suggest that the CNT-OPAMP has a promising potential for low-power, high-speed applications in both analog and mixed-signal nanoelectronic circuits.

High-performance CMOS CCI in a 0.35 $\mu $m CMOS technology and a new all-pass filter application

A differential pair-based, high-performance, first-generation current conveyor is proposed. The proposed circuit is laid out using the Mentor Graphics IC Station layout editor. The performance characteristics have been determined from HSpice postlayout simulations using the Austria Mikro Systeme 0.35 \mu m, 3.3 V process parameters. During the simulations, \pm 1.65 V supply voltages and a 25 \mu A biasing current are used. The power consumption is about 1.12 mW. The circuit also has very high voltage swings on ports X and Y, a very small impedance value on port X, high impedance values on ports Y and Z, and high-valued current and voltage transfer bandwidths. It is shown that the presented circuit can satisfy both the low-voltage/low-power and high-frequency performance current conveyor needs of the analog circuit applications. Furthermore, 2 new all-pass filter circuits as application examples are given and a procedure that can be used to search for the opportunities that would result from the use of the modified current conveyors is presented. Some special circuit topologies and new circuit function possibilities can be obtained by redesigning circuits with modified current conveyors, which is not possible with a standard current conveyor. The proposed approach is expected to allow deeper insight into circuit synthesis using modified current conveyors.

An improved analog electrical performance of submicron Dual-Material gate (DM) GaAs-MESFETs using multi-objective computation

In this paper, new modeling and optimization approaches are proposed to improve the electrical behavior of the submicron Dual-Material-gate (DM) Gallium Arsenide (GaAs)-MESFETs for analog circuit applications. The electrical properties such as current-voltage characteristics, transconductance, output conductance and drain to source resistance of the device have been ascertained and mathematical models have been developed. The proposed mathematical models are used to formulate the objective functions, which are the pre-requisite of genetic algorithm. The problem is then presented as a multi-objective optimization one, where the electrical parameters are considered simultaneously. Analog electrical parameters are also built for the three points sampled from the different locations of the Pareto front, and a discussion is presented for the Pareto relation between the small signal performances (analog behavior) and the design parameters. Therefore, the proposed technique is used to search for optimal electrical and dimensional parameters to obtain better electrical performance of the device for analog circuit applications. The proposed models have been validated by comparison with 2-D numerical simulations (SILVACO); the observed agreement with numerical simulations is quite good.

A Novel BJT Structure Implemented Using CMOS Processes for High-Performance Analog Circuit Applications

In this paper, a novel bipolar junction transistor (BJT) structure is proposed for high matching characteristics and its performance is compared with a conventional BJT structure. Although the proposed BJT matching structure indicates a decrease of collector current density <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$J_{C}$</tex></formula> and current gain <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\beta$</tex></formula> of about 5.36% and 1.02% compared with those of the conventional BJT structure, the matching characteristics of the collector current <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$(A_{\rm IC})$</tex></formula> and the current gain <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(A_{\beta})$</tex> </formula> for the proposed structure are improved by about 31% and 24%. The improved matching characteristic of the proposed structure is believed to be due to the reduced effect of the deep n-well or the reduced current path from emitter to collector.

A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology

Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range ({\pm}400mV), large bandwidth (~50GHz) and low power consumption (~247{\mu}W), while operating at a supply voltage of {\pm}0.9V.

Investigation of the electrical properties of metal–oxide–metal structures formed from RF magnetron sputtering deposited MgTiO3 films

Thin films of MgTiO3 high-k dielectric have been prepared by RF magnetron sputtering deposition at various substrate temperatures. X-ray diffraction, atomic force microscopy were used to characterize the deposited films. Experimental results show that substrate temperature has little effect on the stoichinometry. The electrical properties of MgTiO3 metal–insulator–metal (MIM) capacitors were investigated at various deposition temperatures, Pt/MgTiO3/Pt/SiO2/n-Si, were studied. It is shown that the MgTiO3 (210 nm) MIM capacitor fabricated at 200 °C shows an overall high performance, such as a high capacitance density of ∼1.2 nF/um2, a low leakage current of 1.51 × 10−9 A/cm2 at 5 V, low-voltage coefficients of capacitance, and good frequency dispersion properties. All of these indicate that the MgTiO3 MIM capacitors are very suitable for use in Si analog circuit application or dynamic random access memory (DRAM) cell.

RTDs Based Cellular Neural/Nonlinear Networks with Applications in Image Processing

The resonant tunneling diodes (RTDs) are the quantum tunneling electronics in nano-scale size and have many interesting and valuable properties. Hence, they have been found numerous applications in high-speed digital and analog circuits to decrease the physical size and speed up the processing. This paper addresses the RTD based cellular neural/nonlinear networks (RTD-CNN). To verify its capacity, RTD-CNNs are employed to implement noisy removal, edge extraction and image inversion. A series of simulations demonstrate the effectiveness of the RTD-CNNs in promising applications in image processing.

Multi-objective genetic algorithms based approach to optimize the electrical performances of the gate stack double gate (GSDG) MOSFET

In this paper, a Multi-Objective Genetic Algorithm (MOGA)-based approach is proposed to study and optimize the electrical behavior of Gate Stack Double Gate (GSDG) MOSFET for deep submicron CMOS digital and analog circuit applications. The analytical models, which describe the electrical behavior, of the (GSDG) MOSFET such as OFF-current, threshold voltage roll-off, drain induced barrier lowering (DIBL), subthreshold swing and transconductance have been ascertained. The proposed compact models are used to formulate the objective functions, which are the pre-requisite of multi-objective genetic algorithms. The problem is then presented as a multi-objective optimization one where the subthreshold and saturation parameters are considered simultaneously. The proposed approach is used to find the optimal electrical and dimensional transistor parameters in order to obtain and explore the better transistor performances for analog and digital CMOS-based circuit applications.

Two Stage Operational Amplifiers: Power and Area Efficient Frequency Compensation for Driving a Wide Range of Capacitive Load

Operational amplifiers (OpAmps) have found extensive applications in analog circuits and systems for communications, consumer electronics, controls and signal conversion. Two-stage OpAmps with freguency compensation are popular for driving capacitive loads while ensuring sufficient gain and stability. Frequency compensation technigues have been evolving over the last decades in distinct applications. In particular, power-and-area-efficent two-stage OpAmps capable of driving a wide-range capacitive load are demanded for low-dropout regulators (LDOs) or LCD-panel drivers. Capacitor multiplers (CMs) have emerged as one of the best solutions to implement such kind of OpAmps. This article reviews, for the first time, the state-of the-art CMs for two-stage OpAmps before describing a novel embedded-CM technigue, i.e., the CM as being part of the input stage of the OpAmp, effectively minimizing the physical size of the compensation capacitors while improving the slew-rate with no extra power consumption. Moreover, unlike the classical Miller compensation technique that can lead to an undesired right-half-plane (RHP) zero, a constructive left-half plane (LHP) zero, is created, that can improve the phase margin (PM). Comparing with the state-of-the art current-buffer and CM compensation topologies the proposed solution also features simpler circuitry. The technigue can be further incorporated with a class-AB output stage to speed up the OpAmp's transient re sponses with low guiescent power. A descriptive design example capable of driving capacitive loads ≥ 50 pF is systematically optimized in a 0.35-μm CMOS process. Finally, a few technigues are outlined which allow the combination of current-buffer-based Miller compensation with more sophisticated CMs, or a pole-zero pair (lead network), to further enhance the driving capability of two-stage OpAmps.

Low‐voltage high‐performance current mirrors: Application to linear voltage‐to‐current converter

AbstractCurrent mirror is one of the basic building blocks of analog VLSI systems. For high‐performance analog circuit applications, the accuracy and bandwidth are the most important parameters to determine the performance of the current mirror. This paper presents an efficient implementation of a CMOS current mirror suitable for low‐voltage applications. This circuit combines a shunt input feedback, a regulated cascade output and a differential amplifier to achieve low input resistance, high accuracy and high output resistance. A comparison of several architectures of this scheme based on different architectures of the amplifier is presented. The comparison includes: input impedance, output impedance, accuracy, frequency response and settling time response. These circuits are validated with simulation in 0.18µm CMOS TSMC of MOSIS. In this paper, a linear voltage to current converter, based on the adapted current mirror, is proposed. Its static and dynamic behaviour is presented and validated with the same technology. Copyright © 2009 John Wiley &amp; Sons, Ltd.

A simple CMOS process compatible high performance parallel-stacked spiral inductor for advanced RF analog circuit applications

A high Q on-chip inductor with some unique structures has been fabricated with 0.13 μm CMOS compatible process for the first time. The unique structures including parallel stacked, line via between inter-metal layers, and use the top signal pad as the under path of the inductor instead of conventional bottom signal pad. These structures offer advantages of reducing resistance, high Q value, simple preparing process and small chip area. Experimental results show that the measured peak Q and peak- Q frequency can attain 7.06 and 1.8 GHz, respectively for the structure with four metal layers in parallel, 15 μm in metal width, 5.5 turns in wire number,and an area of 204×240 μm 2. The results have a better potential for advanced mobile communication applications.

Diamond MOSFET: An innovative layout to improve performance of ICs

A new planar MOSFET structure is proposed through a simple layout change, which modifies the gate geometric shape from rectangular to hexagonal in order to use the “corner effect concept” to enhance the resultant longitudinal (parallel) electric field, drift velocity of mobile carriers in the channel, drain current, transconductance, Early voltage and on-resistance in comparison to the equivalent conventional parameters. This paper is conceptual and performs a comparative analyzes between conventional and Diamond Partially-Depleted SOI nMOSFETs by 3D numerical simulations to understand the advantages and disadvantages of this innovative device compared to the conventional counterpart, keeping the same gate area, geometric factor and bias conditions. A simple analytical model for the drain current was proposed and tested for the Diamond transistor. Since we found better results of the Diamond SOI nMOSFETs we believe that, this innovative layout can be a new alternative for analog and digital integrated circuit applications for whatever area it may be needed, without any extra burden to the current technology. This layout approach can also be applied for any planar or 3D transistors technologies.

NMOSFET의 Hot-Carrier 열화현상

본 논문에서는 아날로그 회로에 사용되는 NMOSFET에 대한 Hot-Carrier 열화특성을 조사하였다. 여러 값을 갖는 게이트 전압으로 스트레스를 인가한 후, 소자의 파라미터 열화를 포화 영역에서 측정하였다. 스트레스 게이트 전압의 범위에 따라 계면 상태(interface state) 뿐 아니라 전자와 정공의 포획이 드레인 근처 게이트 산화막에서 확인되었다. 그리고 특히 낮은 게이트 전압의 포화영역에서는 정공의 포획이 많이 발생하였다. 이러한 전하들의 포획은 전달 컨덕턴스 (<TEX>$g_m$</TEX>) 및 출력 컨덕턴스 (<TEX>$g_{ds}$</TEX>)의 열화의 원인이 된다. 아날로그 동작 범위의 소자에서 파라미터 열화는 소자의 채널 길이에 매우 민감하게 반응한다. 채널길이가 짧을수록 정공 포획이 채널 전도도에 미치는 영향이 증가하게 되어 열화가 증가되었다. 이와 같이 아날로그 동작 조건 및 아날로그 소자의 구조에 따라 <TEX>$g_m$</TEX> 및 <TEX>$g_{ds}$</TEX>의 변화가 발생하므로 원하는 전압 이득(<TEX>$A_V=g_m/g_{ds}$</TEX>)을 얻기 위해서는 회로 설계시 이러한 요소들에 대한 고려가 필요하다. This study has provided some of the first experimental results of NMOSFET hot-carrier degradation for the analog circuit application. After hot-carrier stress under the whole range of gate voltage, the degradation of NMOSFET characteristics is measured in saturation region. In addition to interface states, the evidences of hole and electron traps are found near drain depending on the biased gate voltage, which is believed to the cause for the variation of the transconductance(<TEX>$g_m$</TEX>) and the output conductance(<TEX>$g_{ds}$</TEX>). And it is found that hole trap is a dominant mechanism of device degradation in a low-gate voltage saturation region, The parameter degradation is sensitive to the channel length of devices. As the channel length is shortened, the influence of hole trap on the channel conductance is increased. Because the magnitude of <TEX>$g_m$</TEX> and <TEX>$g_{ds}$</TEX> are increased or decreased depending on analog operation conditions and analog device structures, careful transistor design including the level of the biased gate voltage and the channel length is therefore required for optimal voltage gain (<TEX>$A_V=g_m/g_{ds}$</TEX>) in analog circuit.

Pull-In and Release Voltage Design for Nanoelectromechanical Field-Effect Transistors

The Euler-Bernoulli beam equation is solved simultaneously with the Poisson equation in order to accurately model the switching behavior of nanoelectromechanical field-effect transistors (NEMFETs). Using this approach, the shape of the movable gate electrode and semiconductor potential across the width of the channel are derived for the various regimes of transistor operation (before gate pull-in, after gate pull-in, and at the point of gate release). The impact of various transistor design parameters such as the body doping concentration, gate work function, gate stiffness, and as-fabricated actuation gap thickness, as well as source-to-body bias voltage and surface forces, on the gate pull-in and gate release voltages are examined. A unified pull-in/release voltage model is developed to facilitate NEMFET design for digital- and analog-circuit applications.

Physical and Electrical Characterization of Metal–Insulator–Metal Capacitors With $\hbox{Sm}_{2}\hbox{O}_{3}$ and $\hbox{Sm}_{2}\hbox{O}_{3}/\hbox{SiO}_{2}$ Laminated Dielectrics for Analog Circuit Applications

We report the first demonstration of metal-insulator-metal (MIM) capacitors with Sm2O3/SiO2 laminated dielectrics featuring low quadratic voltage coefficient of capacitance (VCC) and high capacitance density for precision analog circuit applications. In comparison with a HfO2 MIM dielectric, the Sm2O3 MIM dielectric is found to show a smaller quadratic VCC and a similar dielectric constant. We also investigated the cancellation of the positive quadratic VCC of Sm2O3 through its combination with a SiO2 layer having a negative quadratic VCC. Thus, MIM capacitors with a Sm2O3/SiO2 laminated dielectric were fabricated with various Sm2O3 and SiO2 thickness combinations. Capacitors with the Sm2O3/SiO2 laminated dielectric exhibit tunable quadratic VCC and high capacitance density. Very low quadratic VCC at various capacitance densities were achieved. The leakage current mechanism is related to Poole-Frenkel emission at a high positive bias. A smaller quadratic VCC is obtained at higher frequencies. We also conducted an extensive physical characterization of Sm2O3 using transmission electron microscopy, X-ray diffraction, and X-ray photoelectron spectroscopy.

Metal-insulator-metal capacitor with high capacitance density and low leakage current using ZrTiO4 film

Thin amorphous and orthorhombic ZrTiO4 film with a high-work-function Ni top electrode has been explored in metal-insulator-metal (MIM) capacitors for analog circuit applications. It has been found that even though the permittivity can be as high as 78.9 for orthorhombic ZrTiO4, the extraordinarily high quadratic voltage coefficient of capacitance (VCC), and leakage current make it ineligible for reliable MIM capacitors. On the other hand, amorphous ZrTiO4 demonstrates a high capacitance density of 29.12 fF/μm2 and a low VCC of 2341 ppm/V2. Because of the amorphous phase and the conduction mechanism of Schottky emission, a low leakage current of 1.3×10−7 A/cm2 at −2 V and a good thermal leakage up to 125 °C has also been obtained. Besides these promising characteristics, amorphous ZrTiO4 holds a great potential for high-performance MIM capacitors not only in its process simplicity but also in the full compatibility with incumbent backend integrated circuit technology.

Hot-Carrier- and Constant-Voltage-Stress-Induced Low-Frequency Noise in Nitrided High- $k$ Dielectric MOSFETs

Understanding and minimization of low-frequency noise (LFN) originating from high- k (HK) gate dielectrics in new generation MOSFETs are of critical importance to applications in RF, analog, and digital circuits. To understand the effect of stress conditions on noise, nMOSFETs were subjected to accelerated hot-carrier stress (HCS) and positive constant-voltage stress (CVS). The additional LFN introduced through stressing was evaluated on nMOSFETs with TiN metal gate and HfSiON gate dielectric. Nitridation of HfSiO gate-dielectric MOSFETs was achieved by either a high-temperature NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> anneal or a lower temperature plasma anneal. Influence of different dielectric nitridation procedures on the stress-induced degradation of transconductance, threshold properties, and LFN was studied. Worst degradation conditions, i.e., V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> , were used for HCS, whereas for CVS, the vertical field was fixed at 10 MV/cm for all transistors to achieve comparable stressing conditions. Plasma-nitrided devices showed less increase in their noise in the linear operation region than the thermally nitrided devices. This difference in noise behavior is attributed to the nitrogen profile across the HK/Si interface and in the bulk of the HK oxide caused by different nitridation techniques. The dielectric defect profile resultant from different annealing techniques was consistent with the spectral form of the observed drain-voltage LFN.

Effective Modulation of Quadratic Voltage Coefficient of Capacitance in MIM Capacitors Using $\hbox{Sm}_{2}\hbox{O}_{3}/\hbox{SiO}_{2}$ Dielectric Stack

We report the first demonstration of metal-insulator-metal (MIM) capacitors with Sm <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> stacked dielectrics for precision analog circuit applications. By using the ldquocanceling effectrdquo of the positive quadratic voltage coefficient of capacitance (VCC) of Sm <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and the negative quadratic VCC of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , MIM capacitors with capacitance density exceeding 7.3 fF/mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , quadratic VCC of around -50 ppm/V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and leakage current density of 1 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at +3.3 V are successfully demonstrated. The obtained capacitance density and quadratic VCC satisfy the technical requirements specified in the International Technology Roadmap for Semiconductors through the year 2013 for MIM capacitors to be used in precision analog circuit applications.

Semiconductor technologies for higher frequencies

An overview of the semiconductor active devices available for 100-GHz and 100-Gb/s applications is given, based on semiconductor properties and device requirements. The most widespread technologies are then described, and then the status of competing technologies is given in two different areas: frequency dividers, which illustrate the suitability of a technology for high-speed digital circuits, and oscillators, which illustrate their behavior in analog circuits applications. The aim of this presentation was to illustrate the variety and potential impact of these evolving technologies with consistently increasing frequency performance. While the improvement of device performance relied for a long time only on the reduction of dimensions permitted by progress in lithography, heterostructures and strain engineering are now powerful means by which to enhance performance, in both speed and power, to a level that opens a door to the 100-GHz and 100-Gb/s application arena.

Tunneling-Based Cellular Nonlinear Network Architectures for Image Processing

The resonant tunneling diode (RTD) has found numerous applications in high-speed digital and analog circuits due to the key advantages associated with its folded back negative differential resistance (NDR) current-voltage (I-V) characteristics as well as its extremely small switching capacitance. Recently, the RTD has also been employed to implement high-speed and compact cellular neural/nonlinear networks (CNNs) by exploiting its quantum tunneling induced nonlinearity and symmetrical I-V characteristics for both positive and negative voltages applied across the anode and cathode terminals of the RTD. This paper proposes an RTD-based CNN architecture and investigates its operation through driving-point-plot analysis, stability and settling time study, and circuit simulation. Full-array simulation of a 128 times 128 RTD-based CNN for several image processing functions is performed using the Quantum Spice simulator designed at the University of Michigan, where the RTD is represented in SPICE simulator by a physics based model derived by solving Schrodinger's and Poisson's equations self-consistently. A comparative study between different CNN implementations reveals that the RTD-based CNN can be designed superior to conventional CMOS technologies in terms of integration density, operating speed, and functionality.