A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology

Ishit Makwana

doi:10.5121/vlsic.2012.3207

Abstract

Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range ({\pm}400mV), large bandwidth (~50GHz) and low power consumption (~247{\mu}W), while operating at a supply voltage of {\pm}0.9V.

Highlights

As predicted by Moore’s law, CMOS manufacturing technology has continued to scale to eversmaller dimensions reaching 32nm [1]
We present a new analog multiplier based on 32nm carbon nanotube field-effect transistor (CNFET) technology with emphasis on high linearity, low power consumption, and high bandwidth
The proposed multiplier circuit has been simulated with Synopsys HSPICE simulator using the 32nm CNFET SPICE model from Stanford University at a supply voltage of ±0.9V [19]

Summary

INTRODUCTION

As predicted by Moore’s law, CMOS manufacturing technology has continued to scale to eversmaller dimensions reaching 32nm [1]. The excellent device performance of carbon nanotube (CNT) is attributed to its near-ballistic transport capability under low voltage bias [2]. Intense research on carbon nanotube (CNT) technology has been performed on digital circuit applications such as logic or memory, as well as radiofrequency (RF) devices for analog applications. CNFET exhibits properties of higher current densities, higher transconductance, lower intrinsic capacitances, as compared to CMOS, which makes CNFET attractive for linear analog circuit applications. Low power and high bandwidth analog circuits can be designed based on CNFET. We present a new analog multiplier based on 32nm CNFET technology with emphasis on high linearity, low power consumption, and high bandwidth. We analyze the performance of the multiplier and compare it with recent works

ANALOG MULTIPLIER DESIGN

Capacitive Divider based Adder-Subtractor Circuit

The Multiplier Core

SIMULATION RESULTS

CONCLUSIONS