Analytical Threshold Voltage Research Articles

Performance and analytical modelling of halo-doped surrounding gate MOSFETs

Halo structure is added to sub-100 nm surrounding-gate metal–oxide–semiconductor field-effect-transistors (MOSFETs) to suppress short channel effect. This paper develops the analytical surface potential and threshold voltage models based on the solution of Poisson's equation in fully depleted condition for symmetric halo-doped cylindrical surrounding gate MOSFETs. The performance of the halo-doped device is studied and the validity of the analytical models is verified by comparing the analytical results with the simulated data by three dimensional numerical device simulator Davinci. It shows that the halo doping profile exhibits better performance in suppressing threshold voltage roll-off and drain-induced barrier lowering, and increasing carrier transport efficiency. The derived analytical models are in good agreement with Davinci.

Analytical Threshold Voltage Model for Double-Gate Schottky Source/Drain Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistor

We modify a theoretically derived model for double-gate silicon-on-insulator metal oxide semiconductor field effect transistor (SOI MOSFET) and establish new analytical threshold voltage model for double-gate Schottky source/drain SOI MOSFET. We show the procedure for deriving this model and present a high accuracy of this model in comparison with the numerical data obtained with a two-dimensional device simulator. We found that we can get the same natural length obtained using a conventional double-gate device and better short-channel effect suppression using double-gate Schottky source/drain SOI MOSFET. Our analytical model can be used for designing Schottky barrier MOSFET with efficiency and accuracy.

Analytical Threshold Voltage Model for Double-Gate MOSFETs With Localized Charges

An analytical threshold voltage model for double-gate MOSFETs with localized charges is developed. From the 2-D Poisson's equation with parabolic potential approximation, a compact threshold voltage model is derived. The proposed model is then verified with a 2-D device simulator. The model can be used to investigate hot-carrier-induced device degradation for various device dimensions and various charge distributions.

Threshold Voltage Model of Short-Channel FD-SOI MOSFETs With Vertical Gaussian Profile

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A novel approximation of 2-D potential function perpendicular to the channel for fully depleted (FD) silicon-on-insulator (SOI) MOSFETs on films with vertical Gaussian profile is proposed in the paper, then an analytical threshold voltage model is derived. The model agrees well with the MEDICI numerical simulation results. It represents a feasible way to find the threshold voltage and gives some reference points in developing new 2-D models for nonuniform FD-SOI devices. </para>

An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYMGAS) surrounding gate MOSFET

A new structural concept, graded channel asymmetric gate stack (GCASYMGAS) SGT has been proposed and a two-dimensional analytical model is developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is shown that incorporation of ASYMGAS and graded channel designs leads to improved short channel immunity and hot carrier reliability. It is also demonstrated that for GCASYMGAS the average electric field in the channel is enhanced which leads to an increase in the electron velocity thereby improving the carrier transport efficiency. Furthermore, the device characteristics have been studied over a wide range of parameters and bias conditions and it is found that GCASYMGAS offers superior characteristics as compared to UD and GC devices. The results so obtained have been compared with simulated data obtained from the device simulator ATLAS 3D and are found to be in good agreement.

Two-Dimensional Analytical Threshold Voltage and Subthreshold Swing Models of Undoped Symmetric Double-Gate MOSFETs

We have developed analytical physically based models for the threshold voltage [including the drain-induced barrier lowering (DIBL) effect] and the subthreshold swing of undoped symmetrical double-gate (DG) MOSFETs. The models are derived from an analytical solution of the 2-D Poisson equation in which the electron concentration was included. The models for DIBL, subthreshold swing, and threshold voltage roll-off have been verified by comparison with 2-D numerical simulations for different values of channel length, channel thickness, and drain-source voltage; very good agreement with the numerical simulations has been observed

Unified model for physics-based modelling of a new device architecture: triple material gate oxide stack epitaxial channel profile (TRIMGAS Epi) MOSFET

A new device architecture triple material gate oxide stack (TRIMGAS) epitaxial channel (Epi) MOSFET for reduced short channel effects (SCEs) at short gate lengths is proposed. The structure has a gate electrode consisting of three different materials, an oxide stack having high-K material on top of an SiO2 layer and an epitaxial channel profile. A two-dimensional analytical threshold voltage and drain current model has been presented. An analysis of subthreshold slope and I–V characteristics has been done for the first time including all regions of operation. The model proposed is capable of modelling various other MOSFET structures: (a) dual material gate stack (DUMGAS), (b) single material gate stack (SIMGAS), (c) straddle-gate/EJ/side-gate MOSFET oxide stack, (d) dual/hetero material gate (DMG/HMG), (e) single material gate (SMG) and (f) triple material gate (TMG), all with and without an epitaxial channel profile. A 2D device simulator, ATLAS, is used over a wide range of parameters and bias conditions to validate the analytical results.

A new analytical threshold voltage model for symmetrical double-gate MOSFETs with high- k gate dielectrics

Based on the fully two-dimensional (2D) Poisson’s solution in both silicon film and insulator layer, a compact and analytical threshold voltage model, which accounts for the fringing field effect of the short channel symmetrical double-gate (SDG) MOSFETs, has been developed. Exploiting the new model, a concerned analysis combining FIBL-enhanced short-channel effects and high- k gate dielectrics assess their overall impact on SDG MOSFET’s scaling. It is found that for the same equivalent oxide thickness, the gate insulator with high- k dielectric constant which keeps a great characteristic length allows less design space than SiO 2 to sustain the same FIBL induced threshold voltage degradation.

Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insu lator (SGOI) MOSFETs

In this paper, a physically based analytical threshold-voltage model is developed for nanoscale strained-Si on silicon-germanium-on-insulator MOSFETs for the first time, taking into account short-channel effects. The model is derived by solving the 2-D Poisson equation in strained-Si and SiGe layers. The effects of various important device parameters like strain (Ge mole fraction in the SiGe layer), body doping, gate workfunction, strained-Si thin film and SiGe layer thickness, etc., has been considered. We have demonstrated that increasing strain in order to enhance device performance can lead to undesirable threshold-voltage rolloff. The model is found to agree well with the 2-D simulation results

A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate analytical model for the threshold voltage of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs is developed by solving the two-dimensional (2-D) Poisson equation. In the proposed model, the authors have considered several important parameters: 1) the effect of strain (in terms of equivalent Ge mole fraction); 2) short-channel effects; 3) strained-silicon thin-film doping; 4) strained-silicon thin-film thickness; and 5) gate work function and other device parameters. The accuracy of the proposed analytical model is verified by comparing the model results with the 2-D device simulations. It has been demonstrated that the proposed model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing equivalent Ge concentration. The proposed compact model can be easily implemented in a circuit simulator

Two-dimensional analytical threshold voltage roll-off and subthreshold swing models for undoped cylindrical gate all around MOSFET

Analytical, physically-based, models for the threshold voltage and the subthreshold swing of undoped cylindrical gate all around (GAA) MOSFETs have been derived at low drain–source voltage based on an analytical solution of the two-dimensional (2-D) Poisson equation (in cylindrical coordinates) with the mobile charge term included. The new model has been verified by comparison with 3-D numerical simulations of devices with different channel lengths and thickness; the observed agreement with the numerical simulations is quite good.

A compact, analytical two-dimensional threshold voltage model for cylindrical, fully-depleted, surrounding-gate (SG) MOSFETs

On the basis of two-dimensional (2D) potential analysis with effective conducting path effect (ECPE), a compact, analytical model for the threshold voltage in cylindrical, fully-depleted, surrounding-gate (SG) MOSFETs is derived. With various depths of the effective conducting path, the minimum channel potential induced by ECPE is used to develop the threshold voltage model. Besides the increased depth of the effective conducting path, both the thin silicon body and gate oxide can reduce the threshold voltage roll-off simultaneously. It is also found that the threshold voltage shift is dependent on the scaling factor of λ1L and characteristic factor of β. Both the high scaling factor and low characteristic factor are preferred to alleviate threshold voltage degradation. This paper not only provides a compact, analytical model but also offers efficient computation and analysis of the threshold voltage for the short-channel cylindrical, fully-depleted, SG MOSFETs.

Two-Dimensional Analytical Threshold Voltage Model of Nanoscale Fully Depleted SOI MOSFET With Electrically Induced S/D Extensions

A new analytical model for the surface potential and the threshold voltage of a silicon-on-insulator (SOI) MOSFET with electrically induced shallow source/drain (S/D) junctions is presented to investigate the short-channel effects (SCEs). Dividing the SOI MOSFETs silicon thin film into three zones, the surface potential is obtained by solving the two-dimensional Poissons equation. Our model includes the effects of the body doping concentration, the lengths of the side and main gates and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide, and also the silicon thin film. Our model results reaffirm that the application of induced S/D extensions to the SOI MOSFET will successfully control the SCEs for channel lengths even less than 50 nm. Two-dimensional simulation results are used to verify the validity of this model, and quite good agreements are obtained for various cases.

Concise Analytical Threshold Voltage Model for Cylindrical Fully Depleted Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors

On a basis of a quasi-2D potential analysis using the effective conducting path effect (ECPE), a concise analytical model for the threshold voltage in cylindrical fully depleted surrounding-gate (SG) metal–oxide–semiconductor field effect transistors (MOSFETs) is derived. With various depths of the effective conducting path, the minimum channel potential Φdeff,min induced by ECPE is used to develop the threshold voltage model. Besides the increased depth of the effective conducting path, a thin silicon body and a decreased oxide thickness can reduce threshold voltage roll-off simultaneously. It is also observed that the threshold voltage shift depends on the scaling factor. A large scaling factor is preferred to alleviate threshold voltage degradation. This paper not only provides a simple analytical model but also offers an efficient analysis of the threshold voltage of the short-channel cylindrical fully depleted SG MOSFETs.

An analytical threshold voltage roll-off equation for MOSFET by using effective-doping model

This paper presents a new analytical threshold voltage roll-off equation for MOSFET by effective-doping model. The short-channel MOSFET is viewed as distributed MOS capacitors with different effective-doping concentration in series. The 2D scale-length approach is adopted to find the potential distribution and the corresponding effective-doping concentration. The source and drain controlled charges are averaged over the channel depletion region to provide more realistic account of the effective-doping concentration. In addition, the lowering of the required band bending and the widening of the channel depletion are considered. As a result, the sub-exponential dependence of the threshold voltage roll-off on channel length is observed. The two governing factors, channel length and drain voltage, can be decoupled in the limit of a mild short-channel effect.

Two-dimensional analytical threshold voltage model for DMG Epi-MOSFET

A two-dimensional (2-D) analytical model of a dual material gate (DMG) epitaxial (Epi)-MOSFET for improved, SCEs, hot electron effects, and carrier transport efficiency is presented. Using a two-region polynomial potential distribution and a universal boundary condition, we calculated the 2-D potential and electric field distribution along the channel. An expression for threshold voltage for short-channel DMG Epi-MOSFETs is also derived. The ratio of gate lengths has been varied to show which gate length ratio gives the best performance. The analytical results have been validated by the 2-D device simulator ATLAS over a wide range of device parameters and bias conditions.

An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect

An analytical threshold voltage model of NMOSFETs including the effect of hot-carrier-induced interface charges is presented. A step function describing the interface charge distribution along the channel is used to account for the hot carrier induced damage, and a pseudo-2D method is applied to derive the surface potential. The threshold voltage model is then developed by solving the gate-to-source voltage at the onset of surface inversion where the minimum surface potential equals the channel potential. Both the drain-induced barrier lowering (DIBL) and body effects are included in the present model as well. The present threshold voltage model is validated for both fresh and damaged devices. The results show that the threshold voltage shifts upward and approaches a maximum value with negative interface charges and shifts downward and reaches a minimum value with positive interface charges as the interface charge region length is increased from zero to the channel length. Model is successfully verified using simulation data obtained from TCAD (technology-based computer-aided design).

An Analytical Model of Short-Channel Effect for Metal–Oxide–Semiconductor Field-Effect Transistor with Insulated Shallow Extension

In this paper, we present an analytical short-channel threshold voltage model without any fitting parameter for the metal–oxide–semiconductor field-effect Transistor (MOSFET) with insulated shallow extension (ISE). Excellent agreements between the numerical simulated results and this model are obtained. Very good suppression of the short-channel effect is observed for this ISE MOSFET. Both the sidewall-oxide thickness and shallow-extension depth play a major role in containing the short-channel effect. The threshold-voltage equation is found by using the effective-doping model. The effective doping is derived from the knowledge of the channel potential. The channel potential is obtained by the scale-length approach to solve 2D Poisson's equation.

A simple 2D analytical threshold voltage model for fully depleted short-channel silicon-on-insulator MOSFETs

In this paper, we propose a simple two-dimensional (2D) analytical threshold voltage model for deep-submicrometre fully depleted SOI MOSFETs using the three-zone Green's function technique to solve the 2D Poisson equation and adopting a new concept of the average electric field to avoid iterations in solving the position of the minimum surface potential. Firstly, we obtain the 2D potential distribution in the Si-film region by using the Green's function technique to solve the 2D Poisson equation. Then, by applying Gauss's law at the Si–SiO2 interface, the initial expression of the threshold voltage is obtained. Eventually, we introduce a modified factor to compensate for the errors resulting from the charge-sharing effect in the derivations of the final threshold voltage model. The proposed model is validated against the results obtained by 2D numerical analysis and experimental data, and excellent agreements are obtained. The proposed model has an explicit expression and can be implemented into the circuit simulator.

A new simplified analytical short-channel threshold voltage model for InAlAs/InGaAs heterostructure InP based pulsed doped HEMT

A new analytical threshold voltage model for InAlAs/InGaAs heterostructure, InP based HEMT has been developed considering the short-channel effect in subthreshold regime. The model is developed following the MESFET analysis, considering fully depleted InAlAs region as two isolated depletions––one due to metal–semiconductor contact and other due to transfer of carriers from InAlAs region to the 2DEG quantum well. Poisson’s equation is solved using Green’s Function technique and the solution is then verified by comparing it with Numerical technique. The 2D threshold voltage obtained from our analysis was found to be in good agreement with 1D threshold voltage for higher gate lengths, thus proving the validity of our model.