Analytical Threshold Voltage Research Articles

Investigation of long channel bulkMOSFETsthreshold voltage model down to 10mKand key analog parameters at 4 K

AbstractThreshold voltage behavior at cryogenic temperatures is dominated by interface traps. This mechanism leads to different trends of the threshold voltage for NMOS and PMOS toward deep cryogenic temperature. This study investigates threshold voltage (Vth) at cryogenic temperatures down to 10 mK for the first time, based on the recently developed physical charge‐based analytical threshold voltage model. To investigate the impact of devices on circuits at low temperatures, crucial MOSFET and analog design parameters, including transconductance (gm), subthreshold swing (SS), linear region current (Ilin) andgm/IDSrelated parameters are characterized and compared from 300 to 4 K. A Discussion on circuit performance and power consumption has been conducted to provide useful insights for low‐temperature CMOS circuit design.

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

AbstractAn analytical drain current model for double gate junctionless accumulation mode negative capacitance field effect transistor (DG‐JAM‐NC‐FET) has been developed, combining the merits of junctionless accumulation mode and negative capacitance effect such as fabrication feasibility, low power dissipation, and reduced degradation in mobility. The novelty manifested in our work is because of the incorporation of the JAM structure in ferroelectric‐based negative capacitance FET. The benefit of JAM over existing FETs is that it combines the benefits of the junctionless transistor (JLT) and conventional FETs. It avoids excessive parasitic resistance due to stronger doping in the source and drain areas, resulting in higher conductivity and better characteristics than JLT. An analytical surface potential and threshold voltage have been developed using Poisson's equation and Landau Khalatnikov's (L‐K) equation. The drain current is then determined by integrating the mobile charge using the Pao–Sah integral. Various critical parameters such as surface potential, gain, capacitance, mobile charge density, drain current, threshold voltage, subthreshold swing, transconductance, and the switching ratio have been assessed extensively by varying ferroelectric layer and channel layer thicknesses, respectively. The ON current increases with the increase in ferroelectric thickness due to the voltage amplification given by the ferroelectric layer, and the switching curve gets steeper. The analytical modeling is done in MATLAB, and its comparison is made with the TCAD numerical simulation. The obtained analytical results and the numerical simulation results correspond well.

Quantitative Analysis of Positive-Bias-Stress-Induced Electron Trapping in the Gate Insulator in the Self-Aligned Top Gate Coplanar Indium–Gallium–Zinc Oxide Thin-Film Transistors

We experimentally extracted the positive bias temperature stress (PBTS)-induced trapped electron distribution within the gate dielectric in self-aligned top-gate (SA-TG) coplanar indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) using the analytical threshold voltage shift model. First, we carefully examined the effects of PBTS on the subgap density of states in IGZO TFTs to exclude the effects of defect creation on the threshold voltage shift due to PBTS. We assumed that the accumulated electrons were injected into the gate dielectric trap states near the interface through trap-assisted tunneling and were consequently moved to the trap states, which were located further away from the interface, through the Poole–Frenkel effect. Accordingly, we quantitatively analyzed the PBTS-induced electron trapping. The experimental results showed that, in the fabricated IGZO TFTs, the electrons were trapped in the shallow and deep trap states simultaneously owing to PBTS. Electrons trapped in the shallow state were easily detrapped after PBTS termination; however, those trapped in the deep state were not. We successfully extracted the PBTS-induced trapped electron data within the gate dielectric in the fabricated SA-TG coplanar IGZO TFTs by using the proposed method.

Threshold Voltage Modeling of Double Gate-All-Around Metal-Oxide-Semiconductor Field-Effect-Transistors (DGAA MOSFETs) Including the Fringing Field Effects

In this paper, an analytical threshold voltage model of double gate-all-around metal-oxide-semiconductorfield-effect-transistors (DGAA MOSFETs) including the fringing field effects is developed. The total fringing capacitance arising due to induced fringing fields in the device is divided into inner, outer and bottom fringing capacitance. A simple expression for each fringe capacitance is developed individually. The 3-D Poisson's equation has been solved in the channel region using the parabolic potential approximation method to develop the surface potential expressions. The effects of fringing capacitances of inner and outer gates which causes charge induction in the source/drain regions have been incorporated within the developed surface potential expressions. The change in potential due to these induced charges of source/drain region along the channel is formulated and added with the developed surface potential expression at both surfaces. The obtained modified surface potential equations have been utilized to derive the expression of the threshold voltage of the device. The performance of the proposed model has been compared with the previously developed model of DGAA MOSFET structure without High-k dielectrics. The effects of variation of device parameters on the threshold voltage have been also analyzed. The accuracy of the proposed model has been verified by numerical simulation results obtained by a device simulator VTCAD from Cogenda Int.

Nanowire reconfigurable FET as biosensor: Based on dielectric modulation approach

In this paper, we have developed analytical surface potential and threshold voltage model of nanowire reconfigurable Field Effect Transistor (FET) which acts as a biosensor to detect the biomolecules, based on dielectric modulation approach. Due to its reconfigurable behavior, it acts as both p-type and n-type depending on the polarity of the biasing and hence find wide spread applications in the field of Programmable Logic Arrays (PLAs). The same is employed here as a bio sensor device with split gates and a cavity for biomolecules immobilization on a thin layer of silicon dioxide as adhesive layer. When the biosensor interacts with the bio targets of the cavity, the electrostatic properties of the device including variation in potential profile and threshold voltage shift get affected and thus have been identified as detection metric in this present work. The characteristic trends of the biosensor are studied with varying height, dielectric constant and charge of the bio-species as polarity of the applied biases change. In addition to this, sensitivity of nanowire RFET is analyzed by assessing the threshold voltage variation which is further compared with equivalent MOSFET biosensor. All the analytical results obtained are corroborated with technology computer-aided-design (TCAD) simulation data to verify the precision of our model.

Analytical threshold voltage and subthreshold swing model for TMG FinFET

ABSTRACTAn analytical modelling of the subthreshold surface potential, threshold voltage (VT) and subthreshold swing (SS) for a triple material gate (TMG) FinFET is presented. The basis of the 3D solution is two separate 2D solutions. The FinFET is separated into two 2D structures: asymmetric triple material double gate (TMDG) and symmetric TMDG MOSFETs. Their potential distributions are obtained by solving the corresponding 2D Poisson’s equations. The potential distribution in TMG FinFET is obtained by a parameter-weighted sum of the two 2D solutions. Utilising the concept of minimum source barrier as the leakiest channel path, the minimum value of the surface potential is developed from the potential model. This leads to the derivations for the threshold voltage and SS. Furthermore, the effects of variation in gate work function and gate length are investigated for analytically developed SS and VT models. Our models are validated against TCAD Sentaurus-simulated results and found to be quite accurate.

Threshold Voltage Model of Total Ionizing Irradiated Short-Channel FD-SOI MOSFETs With Gaussian Doping Profile

This paper investigates the effect of total dose radiation on the electrostatic potential distribution and the related short-channel effects (SCEs) of silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) devices with a vertical Gaussian doping profile. A new approximation of the 2-D potential function perpendicular to the channel for fully depleted SOI MOS field-effect transistors (FETs) is applied in the analytical threshold voltage model derivation. The impact of interface traps and oxide-trapped charge on the electrostatic potential profile, scaling, and SCEs are verified with TCAD simulations. The model agrees well with the experimental extractions of SCE in n-channel MOSFETs.

Threshold Voltage Modelling of Linearly Graded Binary Metal Alloy Gate Electrode with DP MOSFET

Two-dimensional (2D) analytical threshold voltage model for Linearly Graded Binary Metal Alloy (LGBMA) gate electrode with Dielectric Pocket (DP) Metal Oxide Semiconductor (MOSFET) has been developed by solving 2-D Poisson’s equation using evanescent mode analysis technique. In this proposed model, first time the idea of work function engineering is incorporated for DP MOSFET to bring an improvement over different short channel effects (SCEs). In present paper, the expressions for surface potential and threshold voltage are derived along with drain current, transconductance and drain conductance. Moreover, this model also predicts the variations of different SCEs like threshold voltage roll off, Drain-induced Barrier Lowering (DIBL) and sub-threshold swing along the channel length correctly. All analytical results are verified by ATLAS-2D simulator.

Threshold-voltage shift model based on electron tunneling under positive gate bias stress for amorphous InGaZnO thin-film transistors

An analytical threshold-voltage (Vth) shift model of amorphous InGaZnO thin-film transistors (a-IGZO TFTs) under positive gate bias stress (PGBS) is reported in this paper. It is demonstrated that electrons in active layers of a-IGZO TFTs can tunnel into gate insulators when PGBS is applied, and a portion of the tunneled electrons would tunnel back. The transfer distance of the tunneled electrons and the time-dependent electron distribution in gate insulators are analyzed with the back-tunneling effect taken into consideration. Finally the Vth shift under PGBS is predicted and the influences of gate voltage and stress time are discussed. The calculated Vth shift under PGBS shows good consistency with the reported experimental data.

2-D Analytical Threshold Voltage Model for Dielectric Pocket Double-Gate Junctionless FETs by Considering Source/Drain Depletion Effect

This paper proposes an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained by solving 2-D Poisson’s equation using an evanescent mode analysis with suitable boundary conditions. The potential function has then been used for modeling the threshold voltage to investigate the effects of the DP thickness and length on the short-channel effects of the structure. The effects of source and drain depletion regions have been included for improving the accuracy of the model. The model results of DP-DG JLFETs have been compared with the simulation data obtained from the 2-D TCAD ATLAS device simulator.

Performance analysis of junctionless double gate VeSFET considering the effects of thermal variation – An explicit 2D analytical model

The purpose of this paper is to explore junctionless double gate vertical slit field effect transistor (JLDG VeSFET) with reduced short channel effects and to develop an analytical threshold voltage model for the device considering the impact of thermal variations for the very first time. The model has been derived by solving 2D Poisson’s equation and the effects of variation in temperature on various electrical parameters of the device such as Rout, drain current, mobility, subthreshold slope and DIBL has been studied and described in the paper. The model provides a deep physical insight of the device behavior and is also very helpful in contributing to the design space exploration for JLDG VeSFET. The proposed model is verified with simulative analysis at different radii of the device and it has been observed that there is a good agreement between the analytical model and simulation results.

Analytical threshold voltage model for strained silicon GAA-TFET**Project supported by the National Natural Science Foundation of China (Grant No. 61474085).

Tunnel field effect transistors (TFETs) are promising devices for low power applications. An analytical threshold voltage model, based on the channel surface potential and electric field obtained by solving the 2D Poisson’s equation, for strained silicon gate all around TFETs is proposed. The variation of the threshold voltage with device parameters, such as the strain (Ge mole fraction x), gate oxide thickness, gate oxide permittivity, and channel length has also been investigated. The threshold voltage model is extracted using the peak transconductance method and is verified by good agreement with the results obtained from the TCAD simulation.

Analytical threshold voltage modeling of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs

Two dimensional threshold voltage model of ion-implanted strained-Si double-material double-gate MOSFETs has been done based on the solution of two dimensional Poisson’s equation in the channel region using the parabolic approximation method. Novelty of the proposed device structure lies in the amalgamation of the advantages of both the strained-Si channel and double-material double-gate structure with a vertical Gaussian-like doping profile. The effects of different device parameters (such as device channel length, gate length ratios, germanium mole fraction) and doping parameters (such as projected range, straggle parameter) on threshold voltage of the proposed structure have been investigated. It is observed that the subthreshold performance of the device can be improved by simply controlling the doping parameters while maintaining other device parameters constant. The modeling results show a good agreement with the numerical simulation data obtained by using ATLAS™, a 2D device simulator from SILVACO.

An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson’s equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLAS™, a 2-D device simulator from SILVACO.

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

ABSTRACTIn this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.

Analytical model and new structure of the enhancement-mode polarization-junction HEMT with vertical conduction channel

A novel enhancement-mode (E-mode) polarization-junction HEMT with vertical conduction channel (PVC-HEMT) is proposed, and its analytical model for threshold voltage (Vth) is presented. It has two features: one is GaN/AlGaN/GaN double hetero-structure, the other is that source and drain locate at the same side of trench-type MOS gate (T-gate), and the source contacts with the T-gate, which forms vertical conduction channel (VC). The 2-D hole gas (2-DHG) and 2-D electron gas (2-DEG) are formed at the GaN-top/AlGaN and AlGaN/GaN-buffer interface, respectively, forming the polarization-junction. First, the E-mode operation is realized because 2-DHG under the source prevents the electrons injecting from source to 2-DEG, breaking through the conventional E-mode method by depleting 2-DEG under the gate. Second, a uniform electric field (E-field) distribution is achieved due to the assisted depletion effect by polarization-junction. Third, the source reduces the E-field peak at the T-gate side and modulates the E-field distribution. The breakdown voltage (BV) of PVC-HEMT is 705 V and specific ON-resistance (RON,sp) is 1.18 mΩ cm2. Compared with conventional HEMT (C-HEMT), PVC-HEMT has a smaller size due to the special location of the source and T-gate. An analytic threshold voltage model is presented and the analytical results agree well with the simulated results.

Analyzing the effect of gate dielectric on the leakage currents

An analytical threshold voltage model for MOSFETs has been developed using different gate dielectric oxides by using MATLAB software. This paper explains the dependency of threshold voltage on the dielectric material. The variation in the subthreshold currents with the change in the threshold voltage sue to the change of dielectric material has also been studied.

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

A 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.

A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure

A general potential model is proposed for all types of double-gate junctionless FETs (DGJL-FETs), i.e., the symmetric versus asymmetric DG structures and the tied versus untied DG structures. The potential model is obtained with a simple form through a 2-D Poisson’s equation based on the assumption that the vertical channel potential is approximated to a cubic function of the position in order to consider all types of DGJL-FETs. An analytical threshold voltage ( $V_{T})$ equation via the potential model is derived with the gate voltage when the sum of the depletion widths from the front-gate and the back-gate equals the body thickness. The analytic solution of $V_{T}$ shows good agreement with the simulation results down to a channel length $V_{T}$ is analyzed for various device parameters. The back-gate effect of the untied DG structure is also investigated.

Modeling the threshold voltage of PNIN SSOI tunnel field‐effect transistor

AbstractIn this paper, a physically based analytical threshold voltage model for PNIN strained‐silicon‐on‐insulator tunnel field‐effect transistor (PNIN SSOI TFET) is proposed by solving the two‐dimensional (2D) Poisson equation in narrow N+ layer and intrinsic region. In the proposed model, the effect of strain (in terms of equivalent Ge mole fraction), narrow N+ layer and gate dielectric, and so on, is being considered. The validity of the proposed model is verified by comparing the model results with 2D device simulation results. It is demonstrated that the proposed model can correctly predicts the trends in threshold voltage with varying the device parameters. This proposed model can be effectively used to design, simulate, and fabricate the PNIN SSOI TFETs with the desired performance. Copyright © 2015 John Wiley & Sons, Ltd.