Quantitative Analysis of Positive-Bias-Stress-Induced Electron Trapping in the Gate Insulator in the Self-Aligned Top Gate Coplanar Indium–Gallium–Zinc Oxide Thin-Film Transistors

Dae-Hwan Kim,Hwan-Seok Jeong,Dong-Ho Lee,Sunhee Lee,Hyuck-In Kwon,Kang-Hwan Bae,Myeong-Ho Kim,Jun-Hyung Lim

doi:10.3390/coatings11101192

Dae-Hwan Kim, Hwan-Seok Jeong + Show 6 more

Open Access

https://doi.org/10.3390/coatings11101192

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Journal: Coatings	Publication Date: Sep 29, 2021
Citations: 4	License type: CC BY 4.0

Affiliation: Chung-Ang University, Samsung (South Korea)

Abstract

We experimentally extracted the positive bias temperature stress (PBTS)-induced trapped electron distribution within the gate dielectric in self-aligned top-gate (SA-TG) coplanar indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) using the analytical threshold voltage shift model. First, we carefully examined the effects of PBTS on the subgap density of states in IGZO TFTs to exclude the effects of defect creation on the threshold voltage shift due to PBTS. We assumed that the accumulated electrons were injected into the gate dielectric trap states near the interface through trap-assisted tunneling and were consequently moved to the trap states, which were located further away from the interface, through the Poole–Frenkel effect. Accordingly, we quantitatively analyzed the PBTS-induced electron trapping. The experimental results showed that, in the fabricated IGZO TFTs, the electrons were trapped in the shallow and deep trap states simultaneously owing to PBTS. Electrons trapped in the shallow state were easily detrapped after PBTS termination; however, those trapped in the deep state were not. We successfully extracted the PBTS-induced trapped electron data within the gate dielectric in the fabricated SA-TG coplanar IGZO TFTs by using the proposed method.

Highlights

In the last decade, indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) have attracted significant attention because of their excellent electrical properties, low fabrication temperatures, and good large-area uniformities [1,2,3]
Under positive bias temperature stress (PBTS), numerous electrons accumulate near the gate dielectric, and some electrons move toward the gate dielectric and become trapped in the dielectric trap states [7]
They assumed that the trapped electrons in the gate dielectric are the primary reason for the transfer curve shift under PBTS and that electrons are trapped in the trap state only at a single energy level

Summary

Introduction

Indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) have attracted significant attention because of their excellent electrical properties, low fabrication temperatures, and good large-area uniformities [1,2,3]. When used for the backplane of AMOLED displays or digital X-ray detectors, IGZO TFTs are frequently subjected to positive bias temperature stress (PBTS); it is crucial to understand the PBTS-induced instability mechanism in IGZO TFTs. Under PBTS, numerous electrons accumulate near the gate dielectric, and some electrons move toward the gate dielectric and become trapped in the dielectric trap states [7]. The assumptions made in these studies are somewhat problematic They assumed that the trapped electrons in the gate dielectric are the primary reason for the transfer curve shift under PBTS and that electrons are trapped in the trap state only at a single energy level.

Experimental Section

Results and Discussion

Conclusions