Advanced Packaging Solutions Research Articles

2.5- and 3-D TSV Technology Applications and Failure Analysis Challenges

Abstract The semiconductor industry has followed Moore’s law in the last four decades. However, transistor performance improvement will be limited, and designers will not see doubling of frequency every two years. The need for increased performance and further miniaturization has driven the development of advanced packaging solutions, such as fan-in wafer-level chip-scale packaging, fan-out wafer-level packaging, wire-bonded stacked dice, and package-on-package. These technologies are used in mass production and provide significant benefits in form factor but may not give the desired improvement in die-to-die bandwidth. Recently, 3-D integrated circuits (ICs) that employ vertical through-silicon vias (TSVs) for connecting each die have been proposed. It is an alternative solution to existing package-on-package and system-in-package processes. This column addresses some of the challenges in implementing new TSV techniques.

Self Priming Low Stress Aqueous Developable Benzocyclobutene (AD-BCB) Photodielectric Materials for Advanced Wafer Level Packaging

As the semiconductor industry drives to more functionality in smaller and lighter devices, it requires new materials to meet the changing requirements of new and more advanced chip designs and packaging solutions. Photoimagable polymeric dielectric materials are a key building block for wafer level packaging (WLP); these include polyimide (PI), polybenzoxazole (PBO), acrylics, silicones, epoxy-phenolics and benzocyclobutene (BCB). Because of low copper diffusion, low temperature curing, high reliability and low moisture adsorption, BCB was the platform chosen for modification. In this work, we will focus on the development of self priming, low stress, aqueous developable version of BCB, known as AD-BCB. This new photodielectric material has improved mechanical properties of <25MPa film stress value and >28% elongation while maintaining good post develop and post cure adhesion on various substrates including silicon, silicon oxide, silicon nitride, copper, aluminum and epoxy molding compound. Elongation is significantly increased for this positive tone, aqueous developable, photodielectric materials, while film stress and wafer bow are significantly reduced. In addition, this new formulation is self priming and does not require a spin-on adhesion promoter. The material can be cured at as low as 200 °C with lithographic feature size of <10 μm and dielectric constant of 3.0.

On the crack and delamination risk optimization of a Si-interposer for LED packaging

3D-integration becomes more and more an important issue for advanced LED packaging solutions as it is a great challenge for the thermo-mechanical reliability to remove heat from LEDs to the environment by heat spreading or specialized cooling technologies. Thermal copper-TSVs provide an elegant solution to effectively transfer heat from LED to the heat spreading structures on the backside of a substrate. But, the use of copper-TSVs generates also novel challenges for reliability as well as also for reliability analysis and prediction, i.e. to manage multiple failure modes acting combined – interface delamination, cracking and fatigue, in particular. In this case, the thermal expansion mismatch between copper and silicon yields to risky stress situations.To overcome cracking and delamination risks in the vicinity of thermal copper-TSVs the authors performed extensive simulative work by means of fracture mechanics approaches – an interaction integral approach within a simulative DoE and the X-FEM methodology to help clarifying crack propagation paths in silicon. The results provided a good insight into the role of model parameters for further optimizations of the intended thermal TSV-approaches in LED packaging applications.

Adhesive Wafer Bonding Applied for Fabrication of True-Chip-Size Packages for SAW Devices

Surface Acoustic Wave (SAW) filters are key components for mobile communication. In SAW devices mechanical waves propagate on the surface of a piezoelectric bulk material such as LiNbO3 or LiTaO3. SAW components require advanced cavity packaging solutions in order to enable the mechanical wave propagation on the substrate material. Size reduction of SAW filters allows further miniaturization of mobile phones and an extension of their functionality. The mobile communication industry, therefore, demands advanced cavity package technologies to be developed for SAW components. These packages have to offer high performance, high reliability, and low cost while maintaining a form factor as small as possible. To address these requirements EPCOS has developed a Die Sized SAW Package (DSSP), a true chip-size wafer level package for SAW filters. This paper discusses the manufacturing process of wafer-level-packages for SAW-devices with a special focus on the adhesive wafer bonding technology.

(Invited) Development of Advanced Fan-Out Wafer Level Package

Fan-out WLP is one of embedded package processed on wafer level, also a key advanced packages with higher number of I/Os, integration flexibilities. Furthermore, it enables to integrate multiple dies vertically and horizontally in one package without using substrates. Thus, recently Fan-out WLP technology is moving forward to next generation packages, such as multi-die, low profile package and 3D SiP. Not only the electronic packages, Fan-out WLP but also is used for sensor, power IC and LED packages This paper reports developments of next generation Fan-out WLP for advanced packaging solutions.

Carbon Nanotubes in Electronics Interconnect Applications with a Focus on 3D-TSV Technology

High density electronics integration at the system level, supported by advanced packaging solutions, is expected to be the main driving force for the future shrinking of electronics. One recent focus in the field of electronics packaging is the use of through-silicon-via (TSV) to form three-dimensional (3D) integration. A central task in developing 3D-TSV integration is to build reliable and efficient electrical interconnects for signal transfer and power distribution among the stacked layers. Carbon nanotubes (CNTs) are supposed to be a promising material to build future interconnects due to their many attractive electrical and mechanical properties. This paper reviews the state-of-art in CNT integration technology, with a focus on the 3D-TSV interconnect. The simplicity and manufacturability of fabricating and stacking CNT TSVs presented in this paper indicate a great application potential of CNTs as an interconnection material in future 3D integrated electronics.

Ultra High 3D Capacitors Values with High Volume Efficiency and Outstanding Stability

IPDIA's primary effort is to develop innovative 3D technologies to integrate Passive Devices .One of their key technology drivers is the trench high-density capacitor. After introducing the 250nF/mm2 in mass production, it's now the turn to launch outstanding performances with a new worldwide record of 550nF/mm2. With the advanced packaging solutions using very thin dies stacking ,combining a high level of capacitance integration and high volumetric efficiency, this achievement will enable to extend the range of high reliability Silicon Capacitor values up to 10 μF in a package size 3.4mm*2.4mm*1.4mm and even smaller . This paper will provide the details to prove that the former ambitious target of 2 μF/mm3 is now close to reality.

3D & System-in-Package Development with the Redistributed Chip Package (RCP)

Fan-out wafer level packaging (FO-WLP) has become prevalent in past two years as a package option with large number of pin count. As the result of early development, the single die packages with single-sided redistribution has reached the maturity to take off. While the early applications start to pay back the investment on the technology, the developments have shifted to more advanced packaging solutions with System-in-Package (SiP) and 3D applications. The nature of the FO-WLP interconnect along with the material compatibility and process capability of the Redistributed Chip Package (RCP) have enabled Freescale to create novel System-in-Package (SiP) solutions not possible in more traditional packaging technologies or Systems-on-Chip. Simple SiPs using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or a substrate based multi-chip module (MCM). More complex three dimensional (3D) SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMDs, CMOS, GaAs, MEMS, imaging sensors or IPDs gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. The following paper further discusses SiP advantages, applications and examples created with the RCP technology. Rozalia/Ron ok move from 2.5/3D to Passive 1-4-12.

Quasi hermetic packaging for new generation of spaceborn microwave equipment

This paper presents the introduction of the quasi hermetic encapsulation of microwave hybrids for space application through different approaches evaluated at Thales Alenia Space – France. Thanks to the improvement for many years of microwave organic materials, it is now realistic to propose advanced packaging solutions like the chip on board approach with glob top encapsulation of active devices directly bonded on printed circuit boards for space applications. To validate this packaging approach, very significant reliability test-plans have been proposed and performed on the different technological processes and materials in agreement with standard space quality requirements. Results will be presented and a discussion on the nature of the stresses applied during the tests will be proposed.

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

As traditional CMOS scaling becomes progressively more difficult and less beneficial to overall system performance, three-dimensional silicon integration technologies have begun to receive considerable attention. An advanced packaging solution based on a thin silicon carrier has been developed to provide interconnection between integrated circuits (ICs) and other devices at densities. far beyond those of current first-level packaging. The silicon carrier employs fine-pitch Cu damascene wiring, high-density solder interconnections, and through-silicon vias (TSVs). A key enabling technology element is the TSV, which may be naturally scaled to provide vertical interconnection in stacked ICs as well as silicon carriers. In this paper, we discuss the evolution in both TSV design and process flow that has led to TSV technology which produces vias with resistances on the order of 10-20 mΩ and yields on the order of 99.99% at wafer level in a research laboratory environment. Two generalized process approaches to forming TSVs are discussed, the vias-first and the vias-last methods, along with related advantages and potential drawbacks of each. Improvement to these process, flows and structures is afforded by simple changes of via geometry from cylindrical to annular or from annular to multibar. While various TSV metallurgies are reviewed, tungsten is shown to be a nearly optimal choice. Results on via resistance, electrical yield, and current-carrying capacity are covered. The use of electrical modeling to predict structures with superior electrical and mechanical properties is also described.

Polyimide and BeO mini port card performance comparison for CDF run IIb

The new silicon detector design for CDF relies on advanced packaging solutions in order to attain the strict small size and low mass requirements dictated by the experiment's physics program. The silicon strip detector at CDF is composed of overlaying silicon sensors in the form of a barrel around the colliding beam. The electronic instrumentation (sensors, readout, and transceiver chips) is assembled into the staves of this barrel. In this paper we describe the development of the mini port card (MPC). The MPC is located at one of the ends of the stave, and it is responsible for signal translation and repetition from the readout chips to and from the data acquisition system (DAQ). The MPC's development has taken two approaches that use different technologies. One of the approaches uses BeO as the board substrate (BeO-MPC), while the other approach uses a hybrid rigid-flexible polyimide substrate (Poly-MPC). We present test results of pre-production parts, each one assembled with a different MPC packaging technology. Complete thermal and electrical characterization of the MPC is shown, and the advantages and disadvantages of both technologies, as well as their influence in the overall system performance, are presented.