3D & System-in-Package Development with the Redistributed Chip Package (RCP)

Abstract

Fan-out wafer level packaging (FO-WLP) has become prevalent in past two years as a package option with large number of pin count. As the result of early development, the single die packages with single-sided redistribution has reached the maturity to take off. While the early applications start to pay back the investment on the technology, the developments have shifted to more advanced packaging solutions with System-in-Package (SiP) and 3D applications. The nature of the FO-WLP interconnect along with the material compatibility and process capability of the Redistributed Chip Package (RCP) have enabled Freescale to create novel System-in-Package (SiP) solutions not possible in more traditional packaging technologies or Systems-on-Chip. Simple SiPs using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or a substrate based multi-chip module (MCM). More complex three dimensional (3D) SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMDs, CMOS, GaAs, MEMS, imaging sensors or IPDs gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. The following paper further discusses SiP advantages, applications and examples created with the RCP technology. Rozalia/Ron ok move from 2.5/3D to Passive 1-4-12.