Adjacent Channel Power Ratio Research Articles

A Low-Computational-Complexity Digital Predistortion Model for Wideband Power Amplifier.

This paper proposes a Composition Piecewise Memory Polynomial (CPMP) digital predistortion model based on a Vector Switched (VS) behavioral model to address the challenges of severe nonlinearity and strong memory effects in wideband power amplifiers (PAs). To tackle this issue, two thresholds are calculated and used to segment the envelope values of the input signal according to the nonlinear distortion characteristics of the PA. In this approach, a Generalized Memory Polynomial (GMP) model is employed for the lower segment, a Memory Polynomial (MP) model is employed for the middle segment, and a higher-order GMP model is employed for the upper segment. By sharing the fundamental MP among the proposed segmented models and leveraging a design methodology that configures different cross terms, memory depths, and polynomial orders for each segment, this model achieves superior linearization performance while simultaneously reducing the computational complexity associated with model extraction. The experimental results demonstrate that the adjacent channel power ratio (ACPR) of the predistorted PA output signal using the proposed model improves from -36 dBc to -54 dBc, matching the performance of the GMP model. Furthermore, this performance is 0.5 dBc better than the Piecewise Dynamic Deviation Reduction (PDDR) and Decomposed Vector Rotation (DVR) models. Notably, the complexity of the proposed parameter extraction process is 28.8% of the DVR model, 21.79% of the GMP model, and 12.83% of the PDDR model.

Class iCGF–1 Mode Power Amplifier for Enhancing the Linearity of the Traditional Continuous Class F–1 Mode

ABSTRACTIn this paper, the iCGF−1 mode is proposed to compensate the amplitude‐to‐amplitude modulation (AM/AM) distortion of the traditional continuous class F−1 mode while maintaining the high efficiency. The AM/AM profile of the iCGF−1 mode is mathematically expressed simultaneously as a function of the input nonlinearity parameter and conduction angle , which makes the iCGF−1 mode more flexible in controlling the AM/AM profile. The first inflection point of the AM/AM profile can be moved to a higher output power level through theoretical deduction by adjusting the second harmonic source impedance and gate bias voltage to increase the values of and . This flattens the AM/AM profile while the efficiency profile remains almost the same as that of the traditional continuous class F−1 mode. The performance of the iCGF−1 mode is verified through simulation and experimental measurements. The iCGF−1 PA is fabricated with CGH40010F and has a frequency range of 2–2.6 GHz. The drain efficiency is 70.1%–77.9%, and the output power is 41.1–41.7 dBm. The linearity is tested with a 100 MHz 5G NR signal (the peak average power ratio (PAPR) is 8.5 dB) at 2.3 GHz. The worst adjacent channel power ratio (ACPR) is −32.3 dBc without digital predistortion (DPD) and −52.1 dBc with DPD. The results show that the iCGF−1 mode has successfully compensated the AM/AM distortion of the traditional continuous class F mode and maintaining high efficiency.

Formation of CBOC signals with a reduced level of out-of-band radiation

Formulation of the problem. The article considers the issues of choosing low-pass filters with finite and infinite pulse characteristics used to generate CBOC signals with phase manipulation with a reduced level of out-of-band radiation. Purpose. The influence of the filter frequency band on the distortion of CBOC signals in the frequency and time domain is estimated by mathematical modeling. Results. The following filter parameters, peak factor and ACPR (Adjacent Channel Power Ratio) were studied and calculated. Practical significance. The results obtained can be used by developers of local navigation systems.

Analysis and design of hybrid Doherty-Outphasing power amplifier

This paper theoretically analyzes the network phase solution space under Doherty, Outphasing, and hybrid modes. A dual-input wideband Doherty-Outphasing power amplifier (DOPA) design method is proposed. This method can ensure that the output back-off (OBO) amount is further increased based on the OBO amount of Doherty power amplifier. To prove the reliability of the proposed method, a hybrid DOPA power amplifier in the band of 1.7–2.4 GHz with an OBO amount of 12 dB is designed. The experimental results also show that the output power of the hybrid DOPA is 48.6–49.5 dBm in the band of 1.7–2.3 GHz, and the saturation efficiency is 57%–63%. The efficiency at 12 dB, 9 dB and 6 dB OBO is 42%–50%, 46%–59% and 50%–63% respectively. The digital pre-distortion correction is carried out at 1.8, 2.1 and 2.3 GHz frequency points, and the adjacent channel power ratio is lower than -47.7 dBc. Simulation and experiment results can verify the effectiveness and correctness of the proposed method. To the best of our knowledge, it is the first time to achieve such a wide bandwidth to the hybrid DOPA with the proposed design method.

Ultra-Generalized Continuous Class F Power Amplifier with Finite Third-Harmonic Load Impedance

This paper proposes the ultra−generalized continuous class F (UCCF) mode, which combines the influences of the drain current conduction angle and overdriven transistor on the drain current waveform to achieve a broader finite third-harmonic load impedance space. The UCCF mode uses α to describe the magnitude of the drain current conduction angle and pcr to describe the drain current peak-clipped ratio. An analysis of the effects of pcr and α on the linearity and efficiency of the UCCF model is presented, establishing a robust theoretical foundation for achieving a balance between these two characteristics. Additionally, an examination of how pcr and α influence the load impedance design space is conducted, demonstrating that the UCCF mode not only offers a broader finite third-harmonic load impedance space but also expands the fundamental and second-harmonic load impedance design space. For practical validation, a PA with frequency of 2.05–2.65 GHz is designed based on CGH40010F. The test results show that S11 is less than −15 dB, the drain efficiency is 67.0–73.2%, and the output power is 40.1–41.0 dBm. The linearity is tested using a 5G NR (New Radio) signal with a bandwidth of 100 MHz and a peak-to-average power ratio of 8 dB at 2.35 GHz. The worst adjacent channel power ratio (ACPR) is −34.8 dBc without digital predistortion (DPD), and −57.8 dBc with DPD. An average output power (Pave) of around 32.4 dBm and an average DE (DEave) of 34.39% were obtained.

Behavioral Modeling and Digital Predistortion for Power Amplifier Based on the Sparse Smooth Twin Support Vector Regression Method

In this paper, a sparse smooth twin support vector regression (Sparse‐STSVR) model for power amplifier (PA) behavioral modeling is obtained by pruning the kernel matrix based on Cholesky decomposition. Based on the primal smooth twin support vector regression (STSVR) model, the Nystrom approximate matrix of the kernel matrix is found to replace the original kernel matrix, thus simplifying the Newton iterative parameter extraction process of the primal STSVR model and accelerating the convergence of the algorithm. In addition, the new rank approximation kernel matrix has the characteristic of sparse parameters, which further reduces the computational complexity of the feedforward link of the digital predistorter. The 100 MHz 5G New Radio (NR) signal is used for verify the effect of PA modeling and digital predistortion (DPD) experiment. The results show that the proposed method can improve the normalized mean square error (NMSE) by about 2 ~ 3 dB with fewer coefficients compared with the previously proposed machine learning model, and the predistortion linearization effect improves by nearly 3 dB on the adjacent channel power ratio (ACPR), which achieves a good trade‐off between model performance and computational complexity. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

Non-Linear Simulation by Harmonic Balance Techniques of Load Modulated Power Amplifier Driven by Random Modulated Signals

The simulation of the steady state and the non-linear stability of a load modulated power amplifier (LMPA) driven by a random modulated generator, fully performed in the frequency domain by harmonic balance (HB) techniques, is presented. The non-linear microwave circuit and the driving pseudo-random modulated (PRM) generator are integrally defined in the frequency domain. The simulation is implemented and performed using commercially available circuit simulation software. The demodulation of the output signal of the LMPA is implemented with optimally matched filters as software-defined demodulation. The simulated dynamic results of a Quasi-MMIC GaN Doherty power amplifier (DPA) are shown and compared to the measured results with a 16-QAM driving signal at 10 MS/s. The time-domain measurement allows the validation of the new simulation technique through the comparison of both the measured and the simulated error vector magnitude (EVM), the left and right adjacent channel power ratios (ACPRs) versus the average output power. This new simulation is then called pseudo-random modulated harmonic balance (PRM-HB) simulation. The full PRM-HB simulation of an LMPA driven by a random modulated signal, performed in the frequency domain at the design circuit level, results in an advanced simulation tool in the frame of the design of RF circuits and subsystems for telecommunication applications.

Design of an efficiency enhanced wideband Doherty power amplifier based on synthesising of a modified harmonic‐control load modulation network

AbstractA design of a broadband Doherty power amplifier (DPA) using a novel harmonic control network (HCN) is presented. The DPA structure focused on manipulating harmonic components using this new HCN to enhance the bandwidth of operation and power efficiency. The proposed HCN combines a third harmonic suppression network (THSN) with the second harmonic impedance inverter circuit (SHIIC). In the design, the second harmonic component of the main transistor and the peaking transistor are short‐circuited by their associated SHIIC. Additionally, the carefully designed SHIIC and THSN circuit placed between the main and peaking transistors realise open circuit conditions at the third harmonic for both transistors at the saturation state and back‐off regions. Side by side with the aid of the properly designed post‐matching tuned network (PMTN), these harmonic loading conditions make both amplifiers to operate in continuous Class‐F modes with enhanced‐added efficiencies over wideband conditions. As a result, a succession of highly efficient DPA modes can be formed over a continuous frequency range in the full Doherty region, resulting in a reduced‐size enhanced power efficiency wideband DPA. For verification, a wideband DPA operating from 1.1 to 1.8 GHz was designed and implemented using the proposed topology. The measured drain efficiency of the implemented DPA at 6‐dB back‐off is 52.5%–67.5%, while the saturated power across the specified bandwidth is 43–43.7 dBm. The fabricated DPA exhibits an average efficiency of 48.7%–59.4%, when supplied by a 40‐MHz long‐term evolution (LTE) signal with a 7.5‐dB peak‐to‐average power ratio (PAPR). Performing digital pre‐distortion (DPD) improves the adjacent channel power ratio (ACLR) from −25.8 dBc to −47.6 dBc.

Simplified Emulation of Active Load Modulation for a Millimeter-Wave GaN MMIC Doherty Power Amplifier Design

Based on large-signal simulations, this article proposes a simplified method to emulate the active load modulation between the carrier and peaking transistors in a Doherty power amplifier (DPA) design. In contrast to the conventional load–pull method, the proposed method contributes to emulating the active load modulation between the load-modulated transistors with considering their nonlinear interaction. It offers the advantages of predicting the real-world performance of the load-modulated transistors and providing the optimum load-modulation trajectories to be synthesized in a DPA design. To verify the proposed method, a two-way millimeter-wave (mmWave) gallium nitride (GaN) microwave monolithic integrated circuit (MMIC) DPA is designed from 25.5 to 27 GHz. The measured results show that the realized MMIC DPA achieves power-added efficiency (PAE) higher than 30% at saturation, 27% at 6-dB back-off, and 21.5% at 8-dB back-off, with a saturated output power higher than 31.4 dBm across the band. When tested using a 400-MHz modulated signal with digital predistortion (DPD), the MMIC DPA shows adjacent channel power ratio (ACPR) levels better than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 40 dBc over the band.

Vector-switched digital predistortion for concurrent dual-band transmitters with hybrid time-division multiplexing scheme

In a concurrent dual-band digital predistortion (DPD) system, due to the large number of two-dimensional (2D) polynomial-based model coefficients and the existence of cross-modulation terms, the hardware realization usually requires a lot of resources. To alleviate this problem, this paper proposes a hardware-efficient field programmable gate array (FPGA)-based piecewise vector-switched (PVS) DPD method. With the PVS method, a 2D memory polynomial (MP) model with fewer coefficients can be used as a sub predistorter model for each region. Furthermore, a new hybrid time-division multiplexing (HTDM) scheme is proposed for the 2D-MP predistorter architecture, which enables sharing of cross-modulated lookup tables (LUTs) and complex multipliers in a hybrid way. Experimental results show that the proposed method improves the adjacent channel power ratio (ACPR) and normalized mean square error (NMSE) by 18.74 dB and 13.23 dB, respectively, and saves about 30% and 80% of RAM and DSP resources, respectively.

Continuous Class-J/F-1 Mode Asymmetrical Doherty Power Amplifier With Extended Bandwidth and Enhanced Efficiency

This article presents a design method of continuous class-J/F <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-1}$</tex-math> </inline-formula> mode asymmetrical Doherty power amplifier (DPA) using the phase tuning technique. By properly adjusting the phase characteristics of the output matching network (OMN) of the carrier amplifier (CA) and the harmonic impedances of the postmatching network (PMN), the load impedance of CA can be effectively tuned to meet the impedance requirements of continuous class-J and continuous class-F <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-1}$</tex-math> </inline-formula> modes at the power back-off point, which thus extends the bandwidth with enhanced power back-off efficiency. In addition, the proposed DPA can theoretically achieve saturation efficiency of more than 58.7% over the working frequency. Based on the proposed method, a broadband continuous class-J/F <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-1}$</tex-math> </inline-formula> mode asymmetrical DPA operating from 1.3 to 2.5 GHz (63%) is designed and measured. Under the continuous wave stimulation, the measured 9-dB back-off, 6-dB back-off, and saturation efficiencies are 55%–62.5%, 52.4%–65.6%, and 62.5%–81%, respectively. The measured 9-dB back-off and saturation gains are 8.8–11.3 and 7–10.6 dB, respectively. When driven by a 20-MHz long-term evolution (LTE) modulated signal with 9.9-dB peak-to-average power ratio (PAPR), the measured average efficiency is 47%–59% and the adjacent channel power ratio is from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 23.6 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 31.7 dBc.

The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization

A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process.

Spectrally Efficient Pulse Shaping for Beamspace Space Shift Keying in Single-RF ESPAR Systems

A novel spectrally efficient pulse shaping technique for space shift keying (SSK) in single radio frequency (single-RF) antenna systems is proposed. This technique is important since a key issue often overlooked in most single-RF systems, including SSK, is pulse shaping. The proposed pulse shaping technique is based on using an electronically steerable parasitic array radiator (ESPAR). It can avoid the bandwidth expansion arising from switching in SSK while enhancing spectral efficiency (SE) compared to conventional time-limited pulse shaping. In the proposed approach, we pulse shape the parasitic loads of the antennas in the ESPAR by using pulse shaped baseband control voltages to continuously vary the parasitic loads. This is enabled by developing an approximate linear mapping from the baseband control voltages to the ESPAR element currents. Simulation results of the proposed technique are provided, including the continuous-time ESPAR current and its power spectrum density, adjacent channel power ratio, symbol error rate (SER), SE, and energy efficiency (EE). It is shown that the proposed technique can perform spectrally efficient pulse shaping for beamspace SSK and achieve higher SE and EE than time-limited pulse shaping while maintaining the same SER.

Design of a 0.4–3.9-GHz Wideband High-Efficiency Power Amplifier Based on a Novel Bandwidth Extended Matching Network

The design of a multi-octave power amplifier (PA) is presented based on extended continuous Class-B/J (ECB/J) modes in this paper. The wide design space provided by the ECB/J modes has been used as the goal for the design. A unique bandwidth extended matching network that can achieve a broadband impedance matching in the appropriate impedance region by simultaneously manipulating six frequency points is proposed to compensate for the impedance dispersion effect caused by the change of the optimal impedance with the operating frequency in the design of the matching network. To verify the proposed methodology, a wideband PA is designed and fabricated by using a commercial 10-W gallium nitride (GaN) device. The implemented PA achieves a bandwidth of 163% from 0.4 to 3.9 GHz while exhibiting excellent performance of 38-42.3 dBm output power, 57-68% drain efficiency, and 10-13 dB gain. The measured adjacent channel power ratio (ACPR) is lower than -26 dBc at 0.8, 1.5, 2.0, 2.5, 3.0, and 3.5 GHz when the output power is lower than 36 dBm.

A low‐spur harmonic‐cancelation digital predistortion based on neural network for frequency‐hopping HF transmitters

AbstractHigh frequency (HF) transmitter implemented with the multioctave broadband power amplifier (PA) is always faced with the problem of interfering harmonics because of the nonlinearity of the PA. With the harmonic‐cancelation digital predistortion (HC‐DPD) scheme, the harmonics at lower frequencies can be canceled by the injected components and the harmonics at higher frequencies can be filtered out using a low‐pass filter (LPF). However, the HC‐DPD scheme brings the problem of unwanted spurs while lowering the requirements for sampling rate. In this article, a time‐delay neural network (TDNN) model is used to replace the conventional memory polynomial (MP) model in the forward modeling. Theoretical derivation and simulation results validate the effectiveness of the TDNN model in harmonic cancelation and spur suppression. Further, a frequency‐agile neural network (FANN) model is proposed based on the TDNN model. By adding the carrier frequency to the inputs of the network, the trained model can apply to all the trained carrier frequencies and is more friendly to the frequency‐hopping scenarios. Experiments were carried out on a 2–30 MHz HF transmitter testbench. Measurement results show that the harmonic‐to‐fundamental power ratio, the adjacent channel power ratio (ACPR), and the error vector magnitude (EVM) performances were all improved by more than 20 dB. Compared with the MP model, the unwanted spurs can be suppressed by up to 22 dB. In addition, the number of total model coefficients of the proposed FANN model is only 22% of that of the TDNN model under the frequency‐hopping scenario.

Optimized MSA DPD method for improving 5G multiband optical fronthaul performance

AbstractA modified optimized magnitude‐selective affine (OMSA) model‐based digital predistortion (DPD) is presented that introduces the weighting function into our earlier proposed magnitude‐selective affine (MSA) method with an aim to further reduce the complexity overheads without affecting performance compared to the MSA method. This model utilizes a power‐reliant weighted function rather than the summation of MSA quantities for improving the multiband 5G new radio (NR) analog radio over fiber system performance. The OMSA‐DPD method is tested using 5G NR signals which are transmitted over a 10‐km fiber length. The performance of the OMSA‐DPD method is assessed in comparison to MSA and generalized memory polynomial (GMP) methods in terms of adjacent channel power ratio, error vector magnitude, and complexity. The experimental results show that the OMSA‐DPD method achieves better performance with lower complexity compared to the MSA and GMP models, meeting the 3GPP limits.

Attention mechanism based bidirectional LSTM model for broadband power amplifier linearization

AbstractIn this letter, a novel digital predistortion (DPD) model for broadband power amplifier (PA) linearization is proposed, namely Attention Mechanism based Bidirectional Long Short‐term Memory Network (AM‐BiLSTM) model. In order to verify the linearization performance of the AM‐BiLSTM model in digital predistortion process, a 100 MHz bandwidth 5G new radio (5G NR) signal is employed to test a sub‐6G PA operating at 2.6‐GHz. The experimental results show that the adjacent channel power ratio (ACPR) of the PA with AM‐BiLSTM model can be improved by 24 dB which is 6 dB and 3 dB better than the generalized memory polynomial (GMP) model and the Chebyshev polynomials LSTM (CP‐LSTM) model in ref [1], repspectively. Therefore, the proposed AM‐BiLSTM model is very effective for the DPD linearization of broadband PAs.

An Inter-Modulation Oriented Learning Based Digital Pre-Distortion Technique via Joint Intermediate and Radio Frequency Optimization

Pre-distortion is a key technique to compensate for the nonlinear distortions caused by the transmitter in wireless communication systems. Generally, pre-distortion can be classified into digital pre-distortion (DPD) and analog pre-distortion (APD), which focus on optimizing and assessing the nonlinearity in their own areas. In this paper, we propose a new DPD approach to optimize the performance metric of the analog RF-domain (i.e., inter-modulation distortion (IMD) or adjacent channel power ratio (ACPR)) and that of the digital IF-domain (i.e., mean square error (MSE)) simultaneously. To make the joint design feasible, we derive a new hybrid performance metric, where the analog preferred metric is defined in the form of digital signals to bridge the gap between digital and analog signal processing. On top of that, an effective DPD scheme is developed based on a new dual time-delayed neural network (TDNN) learning architecture. The coefficients of the TDNN for power amplifier (PA) modeling can be trained offline with a PA dataset, while those of the TDNN for pre-distortion are obtained adaptively by optimizing the proposed joint design metric. Experimental results show that the proposed scheme is able to significantly improve the IMD/ACPR performance without compromising the MSE, compared to conventional DPD schemes.

On the Viability of Using a Subset of Transmitter- Observation Receivers for Training a Common DPD in Fully Digital MIMO Transmitters

This letter lays the foundation for reducing the required number of transmitter-observation receivers (TORs) for training digital predistortion (DPD) in fully digital massive multiple-input, multiple-output (MIMO) transmitters. Specifically, it investigates the viability of applying the same, common set of DPD coefficients to linearize all RF chains in fully digital massive MIMO transmitters. First, it is shown that if all RF chains are operated at the same output power, the common set of DPD coefficients can be found by simply averaging the coefficients obtained by training each RF chain on its own. This suggests that only a few chains may be needed for training provided the chains are a representative sample. Experimental results are then conducted where one and three chains are used for training. It is found that when training for one chain, significant variations in normalized mean square error (NMSE) and adjacent channel power ratio (ACPR) of up to 9 dB across the chains are realized. For training with three chains, the common set of DPD coefficients can reduce the variation to 1–2 dB. Finally, after over-the-air (OTA) combining, excellent linearization performance is found for three chains.

A Ka-Band CMOS Power Amplifier With OP1dB Improvement Employing a Diode-Connected Analog Linearizer

This paper presents a 30-36 GHz CMOS power amplifier (PA) with a diode-connected analog linearizer dedicated to improving the output power and power-added efficiency (PAE) at 1-dB output compression point (OP1dB). The proposed analog linearizer performs a gain expansion, simultaneously introducing little phase distortion. In addition, a design procedure of the matching network between the analog linearizer and PA is analyzed to mitigate the impact of impedance variation caused by the control voltage and input power. As a proof of concept, the circuit is fabricated in a 65-nm CMOS process with a 0.31 mm2 total area. Measured output power and PAE at OP1dB are > 13.4 dBm and > 12.4%, where maximum improvement of 2.2 dB and 5.9% is achieved at 31 GHz when the analog linearizer is active. The saturated output power of > 16.2 dBm is obtained with the saturated PAE of > 21%. Applying a single carrier 256-QAM signal with a bandwidth of 400 MHz and a peak-to-average power ratio (PAPR) of 10.4 dB, the PA with the proposed analog linearizer can achieve the adjacent channel power ratio (ACPR) of -34 dBc at the output power of 6 dBm.