Adjacent Channel Power Ratio Research Articles

Towards optimization of 5G NR transport over fiber links performance in 5G Multi-band Networks: An OMSA model approach

The application of analog radio over fiber (A-RoF) systems for 5G new radio (NR) multiband waveforms presents challenges, including nonlinearity introduced by the Mach Zehnder Modulator and the dispersion and attenuation of the optical signal over long fiber lengths. To address these challenges, this paper proposes a new version of the magnitude-selective affine (MSA) model, named the optimized magnitude-selective affine (OMSA) model, which incorporates a power-reliant weighting function to improve performance while reducing complexity via Digital Predistortion (DPD). The OMSA model is tested using 5G NR signals at 10 GHz with 50 MHz and flexible-waveform signals at 2.14 GHz with a 20 MHz bandwidth, transmitted over a 10 km fiber length using a Mach Zehnder Modulator and a 1550 nm optical carrier. The performance of the OMSA model is compared to the MSA and generalized memory polynomial (GMP) models in terms of adjacent channel power ratio, error vector magnitude, and complexity. The results show that the OMSA model outperforms the MSA and GMP models in terms of performance reducing the error vector magnitude to 1.9% as compared to 4% and 3% in case of GMP and MSA respectively. Additionally, in terms of complexity measured via coefficients, OMSA is 168 times more efficient as compared to GMP and offers 1.93 times higher efficiency as compared to MSA while maintaining lower complexity. The experimental demonstration of 5G NR multiband waveforms over A-RoF links using the OMSA model represents a significant step towards the practical implementation of high-performance, low-complexity 5G NR systems over fiber-optic links and provides a promising solution to the challenges associated with DPD linearization for A-RoF systems.

Linearity Performance of Derivative Superposition in GaN HEMTs: A Device-to-Circuit Perspective

A significant disconnect exists between the linearity metrics used by device and circuit engineers, degrading the maximum achievable performance in gallium nitride (GaN) technology. A detailed linearity analysis is performed using both device and circuit metrics on GaN devices that employ derivative superposition (DS) to evaluate the amplifier performance under modulated conditions of four different device variants. The limitations of conventional linearity metrics used at the device level, such as the output third-order intercept point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{OI}\text{P}_{\text{3}}$</tex-math> </inline-formula> ) and output 1-dB compression point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{OP}_{\text{1}~\text{dB}}$</tex-math> </inline-formula> ), are examined and compared with communication standard-based metrics, such as the adjacent channel power ratio (ACPR) and error vector magnitude (EVM) to provide best practices for quantifying power amplifier (PA) linearity. It is found that employing more devices in the context of DS primarily improves the input-bias range of the device and not the peak amplifier performance under modulation. Ultimately, this work provides device engineers with a circuit-level perspective on linearity to help design transistors with enhanced RF performance for practical real-world deployment.

Triple-Mode Reciprocal Doherty Power Amplifier With Multi-Band Operation and Extended High Efficiency Range

This article presents the methodology for designing triple-mode Doherty power amplifier (DPA) with multi-band operation and extended high efficiency range. It is illustrated that three different Doherty operation modes can be realized by simply re-setting the gate bias voltages while the DPA circuits keep unchanged. By employing a novel reciprocal gate bias DPA architecture, five operation bands have been achieved by the proposed DPA with larger than 9 dB high efficiency power range. The active load modulation process and theoretical performance of proposed DPA are analyzed in detail for each mode. For verification, a commercial GaN transistors-based DPA is designed and implemented with 1.76-1.96 GHz band in Mode I, 1.13-1.20/2.48-2.58 GHz bands in Mode II and 0.7-0.76/2.34-2.40 GHz bands in Mode III. The fabricated DPA achieves 7.0-10.5 dB saturation gain, 44.18-46.86 dBm peak output power and 41.9%-61.5% back-off efficiency. When stimulated by a 10 MHz long term evolution (LTE) modulation signal with 8.6 dB peaking-to-average ratio (PAPR), the adjacent channel power ratio (ACPR) of the fabricated DPA is better than -45 dBc after digital pre-distortion at 0.73, 1.18 and 1.85 GHz.

Broadband Sequential Load Modulated Balanced Amplifier With Extended Design Space Using Second Harmonic Manipulation

This article presents the design methodology of a broadband radio frequency (RF)-input sequential load modulated balanced amplifier (SLMBA) with extended high-efficiency design space, by introducing the second-harmonic load manipulation over an enlarged range for the control amplifier (CA). The extension of CA load design space not only can provide the time-domain-varying drain current waveform inside the entire design continuum but also allows maintaining high efficiency at output power back-off (OBO) over an extended operation bandwidth. To validate the theory, a broadband SLMBA operating at 2.05–3.65 GHz was designed and fabricated using packaged gallium nitride (GaN) transistors. The implemented power amplifier (PA) attains a measured 45.2–46.8-dBm peak output power. Drain efficiency (DE) of 61.2%–79.7% at saturation and 50.5%–66.2% at 8-dB OBO is achieved throughout the designed bandwidth. When tested with a 100-MHz long-term evolution (LTE) signal with a peak-to-average-power ratio (PAPR) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8$</tex-math> </inline-formula> dB, the proposed SLMBA achieves 50.7%–63.5% average DE over 2.05–3.55 GHz and better than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 45.1 dBc adjacent channel power ratio (ACPR) after digital predistortion (DPD).

Efficient Digital Signal Recovery for Satellite Communications With Active Phased Arrays

In this letter, a transfer learning-assisted (TLA) digital signal recovery (DSR) method is proposed for the linearization of active phased arrays (APAs) for satellite communications to handle the transition to different communication scenarios. The frozen layers of a deep neural network (DNN) are pretrained to extract the main nonlinear characteristics of the APA, and the fine-tuning layers are adopted to achieve prompt update of the regression parameters according to the variations in average input power levels and steering angles. This allows satisfactory reception performance to be maintained in time when the nonlinearity of the APA changes. Experimental results on a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4 \times 4$</tex-math> </inline-formula> APA antenna at 28 GHz show that the proposed method improves the adjacent channel power ratio (ACPR) and the error vector magnitude (EVM) performance. Compared with the existing fully relearned DNN-DSR method, the proposed method achieves almost as good performance with only 1/10 of the data.

FPGA Implementation of a Linearization System for Wideband Envelope Tracking Power Amplifiers

This article focuses on the implementation of a linearization system for envelope tracking (ET) power amplifiers (PAs) in field-programmable gate array (FPGA). The ET PA linearization system includes a slew-rate reduction envelope generator, a RF leakage cancellation system in the supply envelope path and a baseband <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I - Q$ </tex-math></inline-formula> digital predistorter (DPD). This work targets the implementation of an ET PA linearization system on a radio frequency system-on-chip (RFSoC) device running under a demanding baseband sampling frequency of 614.4 MHz, which allows handling communication signals with up to 200 MHz bandwidth, considering a DPD bandwidth expansion by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> . The detail of the FPGA implementation is presented to illustrate the trade-off between hardware resources and linearization performance, i.e., adjacent channel power ratio (ACPR) and error vector magnitude (EVM), under different bit configurations for the arithmetic. The power consumption is also evaluated since it is another relevant performance indicator to be considered in the FPGA implementation of the linearization system.

High Linear and Temperature Insensitive GaAs Power Amplifier Operating at 3.3–3.6 GHz Using a Multi-Feedback Branch Bias Circuit

This letter describes a design of a 3.3–3.6-GHz GaAs heterojunction bipolar transistor (HBT) power amplifier (PA) with high linearity and temperature insensitivity for the fifth-generation (5G) of new radios (NRs). By involving a multi-feedback branches bias circuit, the voltage at the feedback node of the bias circuit can achieve dynamic self-tuning to stabilize the base voltage as the amplifier’s input power grows and stabilize the bias current as the temperature increases as well. A three-stage common source structure PA in the form of a monolithic microwave integrated circuit (MMIC) is designed using a multi-feedback branch bias circuit with a size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times1.2$ </tex-math></inline-formula> mm. Measured with continuous wave (CW) signals, the output 1-dB compression point at 3.3–3.6 GHz is 34 dBm. The linearity of the PA is also evaluated using a 5G-NR 100-MHz 64-quadratic-amplitude modulated (QAM)-orthogonal frequency division multiplexing (OFDM) signal with a 7-dB peak-to-average-power ratio (PAPR). The proposed PA achieves an adjacent channel power ratio (ACPR) less than −49.5 dBc at an average power of 28 dBm with a power-added efficiency (PAE) of 20% without the use of digital pre-distortion (DPD). In the temperature range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 40\,\,^{\circ }\text{C}$ </tex-math></inline-formula> to 120 °C, the variance of bias current, small signal gain, PAE, output power at 1-dB compression point (OP1dB), and ACPR is relatively minor. This design is ideally suited for 5G communication systems due to its high linearity and temperature insensitivity.

Bandpass Filtering Power Amplifier With Wide Stopband and High Out-of-Band Rejection

In this brief, a power amplifier (PA) with excellent integrated filtering characteristics is presented. The designed process is based on a novel impedance transformer (IT) consisting of cascaded coupled-line sections with stubs. The proposed IT generates four transmission zeros (TZs), which not only greatly improves the frequency selectivity, but also improves the second harmonic suppression performance, further enhancing the linearity of the PA. For demonstration, a bandpass filtering PA is designed, fabricated, and measured. The designed PA exhibits both good filtering bandpass response and power amplification. The rejection levels are larger than 59.7 and 69 dB for the lower and higher suppression bands. Meanwhile, the measured drain efficiency (DE) of the constructed PA is 58.5%-73% with a large-signal gain of 8.9-10.2 dB at 1.85-2.1 GHz. Besides, using a 20 MHz long-term evolution signal as the driving signal for the PA, the adjacent channel power ratio is lower than −57.8 dBc.

A Wideband Energy-Efficient Multi-Mode CMOS Digital Transmitter

This article presents a wideband, energy-efficient digital transmitter (DTX) suitable for multi-mode/multi-band wireless communication applications. It features various operation modes comprising Cartesian (Modes-1/-2) and multi-phase (Modes-3/-4) configurations utilizing LO clocks with different duty cycle in the interleaving/non-interleaving configurations. The multi-phase operation compromises polar and Cartesian features by mapping the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I/Q$ </tex-math></inline-formula> signals into two non-orthogonal basis vectors with a 45° relative phase difference and a 3-bit phase selector scheme. The different operation modes are extensively analyzed and compared. Fabricated in a 40-nm CMOS process with an off-chip matching network, the proposed DTX occupies a core area of 0.72 mm2 and delivers 23.18-dBm RF peak power at 2.1 GHz from a 0.95-V supply voltage with drain/system efficiencies of 66.26%/52.59%, respectively. Utilizing a simple memory-less digital pre-distortion (DPD) for a 160-MHz four-channel 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal, the DTX delivers an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P _{\text {Out}}$ </tex-math></inline-formula> of 13.5/11.4/7.7/9.4 dBm, achieving an adjacent channel (power) ratio (ACL(P)R) of better than −42/−40/−40/−38 dBc and an average error vector magnitude (EVM) of −36/−34/−34/−32 dB, operating in Modes-1/-2/-3/-4, respectively. While transmitting a 200-MHz single-channel 256 (1024)-QAM OFDM signal at 2.4 GHz in Modes-1/-4, the average delivered output power is 14.11/9.29 (12.23/7.32) dBm with average drain and system efficiencies of 33.17%/26.3% (23.82%/22.83%) and 24.81%/22.85% (19.34%/18.81%), while the ACLR and EVM are better than −42/−41 (−43/−43) dBc and −34.6/−33.1 (−33.5/−33.9) dB, respectively.

A Distortion-Free All-Digital Transmitter Based on Noise-Shaped PWM

A novel pulse-width modulation (PWM) architecture for all-digital transmitters (ADT) that achieves good in-band and out-band performance with a very low ratio between the modulated signal frequency and the carrier frequency is presented in this paper. The proposed scheme reduces the harmonics leaving only those corresponding to multiples of the carrier frequency, overcoming the spectral limitations of other PWM implementations and relaxing the filter requirements. The binary signal is obtained using a table-based approach with very low computational complexity, mapping the complex I/Q baseband signal to duty cycles of a square wave with low distortion. In addition, a new parallelized noise shaping circuit to reduce the distortion caused by the discretization of the duty-time intervals is presented. The digital radio frequency signal is generated using a high-speed serializer and a standard pulse former. The ADT is simulated under different scenarios to evaluate the influence of time resolution in terms of Adjacent Channel Power Ratio (ACPR) and Error Vector Magnitude (EVM). The transmitter performance is verified by an FPGA implementation using 64-QAM modulated signals, achieving values of ACPR1, ACPR2, and EVM better than −47 dBc, −53 dBc, and −35 dB, respectively, using 64 quantization levels for the PWM signal.

Spur-Free Harmonic Cancelation Digital Predistortion for HF Transmitters

High frequency (HF) transmitter implemented with the multioctave broadband power amplifier (PA) is always faced with the problem of harmonics because of the nonlinearity of the PA. With the previous harmonic cancellation digital predistortion (HC-DPD) scheme, harmonics and the fundamental components, as a whole, are modeled with a uniform memory polynomial (MP) model. Although the harmonics can be well canceled, unwanted spurs can be generated when the nonlinearity order of the MP model exceeds the critical point because of the limited sampling rate. In this letter, a spur-free HC-DPD (SF-HC-DPD) scheme is proposed to suppress the spurs. Without increasing the sampling rate, a novel anti-aliasing MP (AA-MP) model is proposed. With the energy-saving linearization technique, the signal quality and robustness of HF communication can be greatly improved. Measurement results show that the harmonic-to-fundamental power ratio, the adjacent channel power ratio (ACPR), and the error vector magnitude (EVM) performances were all improved by nearly 20 dB. In addition, the unwanted spurs can be suppressed for being below −80 dBc, which is more than 26 dB better than the HC-DPD scheme with the MP model.

A System Approach for Efficiency Enhancement and Linearization Technique of Dual-Input Doherty Power Amplifier

In this paper, we propose an efficient system approach to improve the power efficiency of dual-input Doherty power amplifier (DIDPA) with maintaining its linearity level. An auto-tuning process based on a hybrid heuristic search control (HHSC) is applied to optimally define DIDPA configuration by optimizing its free parameters. Digital predistortion (DPD) is then integrated to linearize DIDPA using an optimal reduced-complexity model based on the segmentation approach. An optimal pruning process of the free parameters, based on hill-climbing (HC) heuristics, is proposed to reduce the HHSC complexity in order to refine the optimal DIDPA configuration. The system approach has been approved by experimental results, in different scenarios, using an LTE 20 MHz signal with a PAPR of 8 dB. DPD linearization under optimal DIDPA configuration improved linearity using a low-complex model with only 30 coefficients, which exhibited an error vector magnitude (EVM) of 2.5% and an adjacent channel power ratio (ACPR) of −50 dB at an averaged output power of 34 dBm. By updating the cost function coefficients and pruning the free parameters, DIDPA exhibited an EVM of 3%, an ACPR of −50 dB, and a drain efficiency of 47% at an average output power of 39 dBm.

Nonlinear and Load-Pulling Effects in an Octave-Bandwidth Transmit Array

This article presents the design and nonlinear analysis of an octave-bandwidth transmit in-phase power combiner feed network. The goal is to evaluate the effect of nonlinearities on the in-phase spatial power combiner figures of merit (FoMs), namely effective isotropically radiated power (EIRP), overall efficiency, and linearity across a wide bandwidth and as a function of active antenna impedance and power amplifier (PA) supply voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\textrm {DD}}$ </tex-math></inline-formula> ). The analysis is showcased on a 6–12 GHz four-element array implemented with electrically small flared horns fed with microstrip-to ridge waveguide transitions, 2-W commercial gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) amplifiers, and an in-phase Wilkinson power splitter. Over-the-air (OTA) measurements show an EIRP of 50 dBm over the octave bandwidth. Adjacent channel power ratio (ACPR) variation over frequency, power, and supply voltage is also measured through OTA and shows a variation of 10 dB over the considered variables.

Behavior Modeling and Digital Predistortion of Mismatched Wireless Transmitters Using Convolutional Neural Networks

In modern wireless compact transmitters, Power Amplifier (PA) behavior is considerably affected by the impedance mismatch between the PA’s output and the antenna’s input. This PA’s output mismatch results in a reflection at the PA–antenna interface. In this brief, reflection-aware PA modeling and digital predistortion (DPD) techniques are proposed to mitigate the negative impact of this mismatch on the forward and reverse models of the PA. An Augmented Convolutional neural network model <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(\boldsymbol{\Gamma }$ </tex-math></inline-formula> ACNN) is proposed to linearize a Doherty PA under different values of the output mismatch using a single set of coefficients. The developed DPD shows robust performance metrics like normalized mean square error (NMSE), and adjacent channel power ratio (ACPR) under diverse complex output mismatch levels.

Digital Linearization of Wideband Envelope Tracking Power Amplifiers for Mobile Terminals

This article presents a low-complexity linearization method to compensate for multisource nonlinear distortion in wideband envelope tracking (ET) power amplifiers (PAs) for 5G new radio (NR) mobile terminals. The proposed linearization approach consists in an envelope leakage cancellation (ELC) system operating in the dynamic supply path and a 2-D digital predistortion (2-D-DPD) linearizer acting on the baseband complex modulated signal. In a first step, an envelope generalized memory polynomial (EGMP) behavioral model is proposed to compensate for the unwanted radio frequency (RF) leakage that appears at the output of ET modulator (ETM). Then, a baseband 2-D-DPD linearizer based on a slow envelope-dependent generalized memory polynomial (SED-GMP) behavioral model is used to further enhance the linearization performance. The proposed method is validated on a system-on-chip (SoC) ET PA board for mobile applications. The reported experimental results show how the proposed digital linearization approach can mitigate the linearity and efficiency trade-off in ET PAs. Consequently, the out-of-band linearity requirement of −36 dBc of adjacent channel power ratio (ACPR) is met for 5G-NR test signals with bandwidths ranging from 60 to 200 MHz at 2.55 GHz (band B41), with an overall ET PA power efficiency ranging from 10.1% and up to 16.5%, depending on the signal bandwidth.

Digital Signal Recovery With Transmitter Nonlinear State Tracking for Satellite Communications

This brief proposes a digital signal recovery (DSR) method to compensate the nonlinear distortion introduced by power amplifiers (PAs) under dynamic nonlinear operating states. Unlike conventional PA linearization methods that extract the nonlinearity based on the baseband I/Q PA input and output signal samples, the proposed method attempts to derive the memory polynomial (MP) model parameters based on PA operating states using a deep neural network (DNN). This method allows the receiver to achieve DSR by tracking the operating states of the PA effectively with a few telemetry data. Validation results from simulations and experiments based on a GaN PA operating at 3.5 GHz reveal that the proposed method can maintain satisfactory DSR performance in terms of adjacent channel power ratio (ACPR) and error vector magnitude (EVM) while the transmitter PA is operating with fluctuating average input/output power, supply voltage, and bias voltage. The training data size and time are further reduced by using a transfer learning (TL) approach.

Artificial Intelligence-Based Power-Temperature Inclusive Digital Predistortion

This article investigates the effects of the average power variation and the ambient temperature on the behavioral modeling and predistortion of high-power amplifiers concurrently. The measurement results showed that in addition to the average power variation, the behavior of a high-power PA is a function of ambient temperature as well. This article proposes a novel smart digital predistortion (DPD) model that considers both average power variation and temperature (PTI-DPD). The PTI-DPD is implemented using artificial intelligence-based model and it benefits from sets of data formats containing the signal, its delayed versions, average power variation, and ambient temperature. The developed architecture provides an uninterrupted linearization across the ambient temperature and average power variation span without need for a continues feedback path or multiple models. A series of measurements have been conducted to study the PTI-DPD performance across the temperature and average power range. According to the results, the PTI-DPD achieves an average of −48.5 dBc adjacent channel power ratio across the average power and temperature span.

Digital Predistortion Combined with Iterative Method for MIMO Transmitters

In this article, an auxiliary module is proposed to mitigate the crosstalk effect in multiple input–multiple output (MIMO) transmitters. Other branches do not need considering when linearizing the local branch, which reduces the complexity of the auxiliary module, and some branches can be linearized selectively to make the module application more flexible. In the end, the feasibility of the proposed algorithm is verified through the experimental platform. Experimental results demonstrate that for a 2 × 2 MIMO transmitter with −20 dB nonlinear crosstalk, the proposed DPD improves the adjacent channel power ratio (ACPR) more than 16 dB, and normalized mean square error (NMSE) more than 12.8 dB, which has similar performance to the PH model. The predistorter can be implemented with fewer coefficients by separating the crosstalk from the nonlinearity, enabling the technique to be used in 5G massive MIMO scenarios.

Design of a broadband Doherty power amplifier with a modified load modulation network

This article proposes a modified load modulation network (LMN) to adjust the structure of the traditional Doherty power amplifier (DPA) by changing one λ/4 microstrip line at the output of the main power amplifier into two in the traditional DPA and connecting a terminal open-circuit λ/2 line at the junction point which can reduce the frequency dispersion effect to achieve expanding bandwidth while maintaining saturation efficiency and back-off efficiency. A 2.6–3.6 GHz DPA is designed and fabricated for verification. The measured results show that the saturated output power is 42.5–44 dBm and the saturated efficiency is between 63% and 69% in target band with a gain from 8.5 to 9.5 dB. At 6 dB output power back-off, the drain efficiency is 44%–50%. And the adjacent channel power ratio (ACPR) is better than −32 dBc.

A Three-Level RF-PWM Method Based on Phase-Shift Control and MPWM for ADTx

A radio frequency pulse width modulation (RF-PWM) scheme based on phase-shift control and mapping PWM (MPWM) is described. Pulse coding is the key to improving the coding efficiency, flexibility, and configurability of the all-digital transmitter (ADTx). To solve the problem that the real-time performance of the system is limited by the time resolution, the phase-shift control principle is adopted to constrain the output pulse state. It decomposes the original signal into two phase-modulated constant envelope signals, and directly converts the two-level pulse waveform by MPWM. Finally, the fast generation of the three-level digital RF modulated signal is completed by vector synthesis. In this way, the rear power amplifier can be directly driven, and the difficulty of physical implementation is greatly reduced. Different from the traditional mapping strategy of traversal search, the proposed scheme does not require complicated error calculation and comparison. Simulation and offline experiments show that the proposed scheme has better comprehensive performance than other mapping schemes. For 16QAM modulated signals at a 300 MHz carrier, the proposed scheme can achieve nearly 70% coding efficiency (CE), less than −50 dBc, and 1% adjacent channel power ratio (ACPR) and error vector magnitude (EVM).