Abstract
In a concurrent dual-band digital predistortion (DPD) system, due to the large number of two-dimensional (2D) polynomial-based model coefficients and the existence of cross-modulation terms, the hardware realization usually requires a lot of resources. To alleviate this problem, this paper proposes a hardware-efficient field programmable gate array (FPGA)-based piecewise vector-switched (PVS) DPD method. With the PVS method, a 2D memory polynomial (MP) model with fewer coefficients can be used as a sub predistorter model for each region. Furthermore, a new hybrid time-division multiplexing (HTDM) scheme is proposed for the 2D-MP predistorter architecture, which enables sharing of cross-modulated lookup tables (LUTs) and complex multipliers in a hybrid way. Experimental results show that the proposed method improves the adjacent channel power ratio (ACPR) and normalized mean square error (NMSE) by 18.74 dB and 13.23 dB, respectively, and saves about 30% and 80% of RAM and DSP resources, respectively.
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