Adder Architectures Research Articles

A process-tolerant low-power adder architecture for image processing applications

The aggressive CMOS technology scaling in the sub-100-nm regime leads to highly challenging VLSI design due to the presence of unreliable components. The delay failures in arithmetic units are increasing rapidly due to the increased effect of process variation (PV) in scaled technology. This paper introduces a novel process-tolerant low-power adder (Prot-LA) architecture for error-tolerant applications. The proposed Prot-LA architecture segments the operands into two parts and computes addition of the upper parts in carry-propagate, whereas it computes the lower parts in a carry-free manner. In the Prot-LA, the number of bits in carry-propagate and carry-free additions can be reconfigured based on the amount of PV. An on-chip PV detector is embedded to determine the PV severity. Because of this reconfigurability, the proposed adder completes the carry propagation with minimum error even under severe process variation. The simulation results show that proposed Prot-LA provides 19.9 % reduced power consumption over the state-of-the-art approximate adder. The efficacy of the proposed adder is demonstrated in the real application by designing an image scaling processor (ISP). The simulation results show that the Prot-LA embedded ISP consumes 7.75 % reduced energy with 2.43 dB higher PSNR over the existing approximate adder embedded ISP.

RTL Design, Verification and Synthesis of Secure Hash Algorithm to implement on an ASIC Processor

In this project we are comparing different architectures and adding the features that increases the efficiency of our architecture. Few of them are including multiplexers in the message digester, using different adder architectures in the required places, reducing the critical path by breaking the longest path and making them to operate parallelly. Use of multiplexers reduces the number of registers required in the message expander. It simply transfers the output of expander to compressor block in every clock cycle. Whenever the number of cycle is greater than 16, the multiplexer switches the select line so that the computed message digest to send as output to the compressor. Using of a carry save adder and adder array takes lesser time to perform addition than a pair of adders array. Finally we all know that reducing the critical path reduces the overall operation time and hence increases the efficiency. Considering all these factors in the design we are designing the microarchitecture for SHA-256 algorithm and obtain the RTL code for that architecture. We have also verified the design by designing a test-bench, and finally synthesized the design.

Fast Montgomery modular multiplier for Rivest–Shamir–Adleman cryptosystem

A high-speed Montgomery modular multiplier is proposed in this study. This multiplier requires binary input and also generates a modular product in binary form. To speed up the process of multiplication, intermediate operands of the multiplier are kept in carry-save form. This multiplier employs a two-level carry-save adder architecture to keep intermediate operands in carry-save form. This multiplier also employs a look-ahead carry unit (LCU) for conversion of the final output from carry-save form to binary form. LCU is also utilised for pre-computation of intermediate operands. Format conversion and pre-computation require additional clock cycles. In general, each cycle of the Montgomery multipliers involves addition and shift operation followed by computation of the following quotient. The proposed multiplier adds and shifts as well as computes the following two quotients simultaneously to minimise the critical path delay. In addition, the proposed multiplier combines two iterations, which require additional intermediate operands. In this way, the execution time and the number of clock cycles required for multiplication are minimised significantly and extra clock cycles required for format conversion and operand pre-computation can be overlooked. Experimental results show that the proposed approach can achieve significant speed and throughput improvement as compared to previous multipliers.

Novel Efficient Circuit Design for Multilayer QCA RCA

The novel emerging technology, QCA technology, is a candidate for replacing CMOS technology. Full Adder (FA) circuits are also widely used circuits in arithmetic circuits design. In this paper, two new multilayer QCA architectures are presented: one-bit FA and 4-bit Ripple Carry Adder (RCA). The designed one-bit multilayer FA architecture is based on a new XOR gate architecture. The designed 4-bit multilayer QCA RCA is also developed based on the designed one-bit multilayer QCA FA. The functionality of the designed architectures are verified using QCADesigner tool. The results indicate that the designed architecture for 4-bit multilayer QCA RCA requires 5 clock phases, 125 QCA cells, and 0.17 μm2 area. The comparison results confirm that the designed architectures provide improvements compared with other adder architectures in terms of cost, cell count, and area.

Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters

Nowadays, multiple-error occurrence because of multiple transient faults is highly probable in digital circuits especially used in outer space environments. Therefore, concerning such applications, the processing systems performing operations such as addition and multiplication are of great importance and should be redesigned, properly. In this paper, some multiple-error resilient carry look-ahead adders are proposed more efficient than the existing designs. In this manner, at first, two new customized fault-tolerant voters are proposed and analyzed to be used for multiple-error correction/detection in the carry look-ahead adders utilizing a distributed partial triple modular redundancy along with a parity prediction scheme. Then, the new voters are exploited and incorporated into two types of grouped carry look-ahead adder architectures to obtain different designs with a compromise between the area overhead and reliability. Simulation results show that, as well as a complete single error correction/detection, the proposed voters lead to 8–15% area overhead reduction in different carry look-ahead adders while increasing multiple-error correction probability up to 17% and 26% utilizing the first and second proposed voters, respectively, compared to the best existing design. Furthermore, the total multiple error correction/detection probability is improved in different adder architectures in many cases.

PERFORMANCE ANALYSIS OF FULL ADDERS IN CIC DECIMATION FILTER

This article presents analysis of various full adder architecture on Cascaded Integrator-Comb (CIC) filter of delta-sigma ADC. The structure of CIC filter consists of an integrator and a differentiator stage that is built from a cascaded full adder and delay element. Since each of the element within CIC filter has its own low-power architecture, full adder is one of the block that consumes huge amount of power compared to others. In this paper, four different type of full adder’s architecture is designed and simulated with CIC decimation filter. There are 28T conventional, pseudo-NMOS adder, 16T hybrid adder and modified 14T hybrid adder. The performance parameters such as delay, total power dissipation and power delay product (PDP) of CIC filter were compared. This analysis shows that 16T hybrid full adder CIC filter has reduced up to 38.15% of power consumption and 39.18% of power product delay compared to conventional adder. Hence, a complete 1-bit third order of 16T hybrid adder CIC filter is implemented with size area of 118.23µm × 22.38µm.
 Keywords: Delta-sigma ADC, Low-power, CIC decimation filter, Full adder

Analysis, Modeling and Optimization of Equal Segment Based Approximate Adders

Over the past decade, several approximate adders have been proposed in the literature based on the design concept of Equal Segment Adder (ESA). In this approach, an $N$ -bit adder is segmented into several smaller and independent equally sized accurate sub-adders. An $N$ -bit ESA has two primary design parameters: (i) Segment size ( $k$ ), which represents the maximum length of carry propagation; and (ii) Overlapping bits ( $l$ ), which represents the minimum number of bits used in carry prediction, where $1 \leq k and $0 \leq l . Based on the combinations of $k$ and $l$ , an $N$ -bit ESA has $N(N-1)/2$ possible configurations. In this paper, we analyse ESAs and propose analytical models to estimate accuracy, delay, power and area of ESAs. The key features of the proposed analytical models are that: (i) They are generalized, i.e., work for all possible configurations of an $N$ -bit ESA; and (ii) They are superior (i.e., estimate more accurately) or at par to the existing analytical models. From the proposed analytical models, we observe that in an $N$ -bit ESA, there exist multiple (more than one) configurations which exhibit similar accuracy. However, these configurations exhibit different delay, power and area. Therefore, for a given accuracy, the configurations which provide minimal delay, power and/or area need to be known apriori for efficient, intelligent and goal oriented implementations of ESAs. In this regard, we present an optimization framework that exploits the proposed analytical models to find the optimal configurations of an $N$ -bit ESA. Further, we know that accuracy of an ESA does not depend on the adder architecture used to implement it, however, its delay, power and area depend significantly. Consequently, the optimal configurations vary with adder architectures used to implement the ESA. In order to cover a wide range of adders, we consider three types of adder architecture in our analysis: (i) Architectures having smaller area ( $O(N)$ ); (ii) Architectures having smaller delay ( $O(log_2N)$ ); and (iii) Architectures having in-between delay ( $O(N/4)$ ) and area ( $O(2N)$ ).

An Efficient Implementation of Hybrid Carry Select Adder Using Parallel Prefix Addition and Binary to Excess 1 Conversion

One of the fastest adder architecture among the prevailing adder architectures. Adders are digital logic devices that add binary numbers together. They are commonly used as a component in an Arithmetic Logic Unit which itself is a component in Central Processing Unit. As a result any electronic device that has a Microcontroller or a CPU such as smart thermostats, digital alarm clock, digital wrist watches, and digital bathroom scales etc use adder circuit. In this work, we present an 8 bit hybrid Carry Select Adder architecture. It employs Parallel prefix addition using Kogge stone adder structure, Brent Kung adder structure, Han Carlson Adder structure and Ladner Fischer adder structures. It also employs Binary to Excess 1 code converter along with parallel prefix adders. Affirmation of the suggested design completed using Verilog code and simulated using Xilinx ISE 14.7 and the power, area and delay results were calculated using Cadence software. Comparisons with existing conventional adder architecture certify its better quality. The experimental analysis probes that the recommended hybrid carry select adder results threefold advantages in regards with speed, area and power.

A High-Throughput Architecture for the SHA-256/224 Compliant With the DSRC Standard

This article presents a word serial retimed architecture for the SHA-256/224 algorithm. The architecture is compliant with the dedicated-short range communication for safety message authentications. We elaborate three-operand adder architectures suitable for field programmable gate array implementation. Several transformation techniques at the data-flow-graph level have been used to derive the architecture. Synthesis results show that the architecture has high throughput/ slice value compared with state-of-the-art SHA-256 implementations. The article also promulgates a comparison between high-level synthesis and RTL design.

Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e., critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry Cut-Back Adder (CCBA), in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach prevents the logic activation of the carry chain, improving performance and energy efficiency while guaranteeing low worst-case errors. A design methodology is presented along with implementation, error optimization, and design-space minimization. The CCBA is proven capable of extremely high accuracy while displaying significant circuit savings. For a worst case precision of 99.999%, energy savings up to 36% are demonstrated compared with exact adders. Finally, an industry-oriented comparison of 32-bit approximate and truncated adders is carried out for mean and worst-case relative errors. The CCBA outperforms both state-of-the-art and truncated adders for high-accuracy and low-power circuits, confirming the interest of the proposed concept to help building highly-efficient approximate or precision-scalable hardware accelerators.

Design and Implementation of High Speed Area Efficient Carry Select Adder Using Spanning Tree Adder Technique

In this paper, we propose Carry Select Adder (CSLA) architecture with parallel prefix adder. Instead of using 4-bit Brent Kung Adder (BKA), another parallel prefix adder i.e., 4-bit spanning Tree (ST) adder is used to design CSA. Because Adders are key element in digital design, which are not only performing addition operation, but also many other function such as subtraction, multiplication and division. A Ripple Carry Adder (RCA) gives the most complicated design as-well-as longer computation time so that we may gone for parallel prefix adders. This time critical application we use Spanning tree parallel prefix adder to drive fast results but they lead to increase in area. Proposed Carry Select Adder understands between RCA and BKA in term of area and delay. Delay of Existing adders is larger therefore we have replaced those with Brent Spanning Tree parallel prefix adder which gives fast result. This paper describes comparative performance of 4-bit RCA and 4-Bit BK parallel prefix adders with Our Proposed Spanning Tree adder based carry select adder designed using Xilinx ISE tool.

Shape and Positional Anisotropy Based Area Efficient Magnetic Quantum-Dot Cellular Automata Design Methodology for Full Adder Implementation

Magnetic quantum-dot cellular automata (MQCA) based computation started emerging as the Moore's law approaching towards its end. Number of nanomagnets and the area occupancy are major constraints in materializing this MQCA-based digital arithmetic circuit design. In this letter, we propose a design methodology and demonstrate the hybrid approach of using slant edged input and 45 $^\circ$ aligned nanomagnets for optimized binary full adder design. Asymmetric shape anisotropy nanomagnets pave the way for standalone inputs, whereas positional anisotropy reduces the signal loss in transmission of data and enables lossless information propagation. This complementary property of both shape and positional anisotropy leads to exploiting the energy minimization nature of nanomagnets, reducing the design footprint. Further, to enable the multipurpose scaling, horizontal and vertical layouts of the nanomagnetic computing design of full adder has been proposed. Our proposed nanomagnetic adder architecture leads to 28% reduction in the total number of nanomagnets compared to the state of the art design, leading to an area efficient architectural design.

VLSI Implmentation of a Fast Kogge-Stone Parallel-Prefix Adder

This paper presents a VLSI implementation of a high speed Kogge-Stone adder (KSA) using 0.18µm process technology. The adder is known to be one of the fastest adder architectures, and this is validated through a comparison with other adder architectures including the standard ripple carry adder and the carry look ahead adder. Furthermore, our KSA adder is also compared with a default optmized adder from the Artisan standard cell library. The adders are compared for bit widths of 8, 16, and 32. The adders are designed using Verilog and synthesized using both front-end and back-end tools, with complete validation and verification stages, including analysis for performance, power, and area. Results show that in terms of performance, KSA results in the lowest propagation delay with almost constant delay for all bit widths, with up to 70% less delay as compared to all other architectures. Area and power penalty is found to also increase by roughly 59%. In terms of energy usage, the KSA adder results in up to 64% less. In the case when speed and energy are critical, this fast and energy efficient KSA adder can be readily integrated into custom VLSI designs.

Novel design for a memristor-based full adder using a new IMPLY logic approach

This paper presents and evaluates a novel approach based on material implementation to improve the performance of a 1-bit memristor-based full adder. In addition, two new efficient architectures are presented and evaluated for an 8-bit memristor-based full adder, serial memristor-based full adder and parallel-serial memristor-based full adder. Using the proposed approach, the number of required steps to accumulate the sum and carry-out in the proposed serial and parallel-serial 8-bit memristor-based full adder architectures is 168 and 56, respectively. Moreover, the number of required memristors in the proposed serial and parallel-serial memristor-based full adder architectures is 19 and 33, respectively. The evaluation results show that both delay and density are improved in the proposed architectures compared to other memristor-based full adder architectures.

Investigations on performance metrics of FINFET based 8- bit low power adder architectures implemented using various logic styles http://www.indjst.org/index.php/indjst/article/view/111071 1489988072

Objectives: To reduce the leakage power dissipation and minimize the propagation delay, a Fin FET based 8-bit adder architecture is constructed. The performance metrics of these structures are calculated over a range of temperatures and are compared with the MOSFET based 8-bit adder architecture. Various logic styles are utilized for constructing the adder. Method/Analysis: A Ripple carry adder structure is employed. The existing adder architecture is constructed using 90nm MOSFET technology. The proposed adder architecture is constructed using 32nm FINFET technology. The various logic styles employed are Complementary Metal-Oxide Semiconductor logic (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate logic (TG) and Gate Diffusion Input logic (GDI). Cadence Virtuoso is used for designing purpose and simulation is performed using Spectre. Findings: Key performance metrics like static power, dynamic power, leakage power, delay and power delay product are calculated. The dynamic power of MOSFET architecture ranges from 7.42µW to 882.6µW. The dynamic power of FINFET architecture ranges from 0.407nW to 156.2nW. The static power (inputs at high logic level) of MOSFET architecture ranges from 0.001µW to 945.76µW. The static power (inputs at high logic level) of Fin FET architecture ranges from 0.725pW to 170.4nW. The static power (inputs at low logic level) of MOSFET architecture ranges from 0.94nW to 1.68mW. The static power (inputs at low logic level) of Fin FET architecture ranges from 0.127pW to 305.3nW. The leakage power (inputs at high logic level) of MOSFET architecture ranges from 1.27nW to 134.7µW. The leakage power (inputs at high logic level) of Fin FET architecture ranges from 0.36pW to 24.77nW. The leakage power (inputs at low logic level) of MOSFET architecture ranges from 0.54nW to 139.9µW. The leakage power (inputs at low logic level) of Fin FET architecture ranges from 0.15nW to 227.6nW. The delay of MOSFET architecture ranges from 0.344µs to 0.46µs. The delay of Fin FET architecture ranges from 0.19µs to 0.28µs. The power delay product of MOSFET architecture ranges from 2.66 to 405.99. The power delay product of Fin FET architecture ranges from 0.83 to 29.67. Novelty/Improvements: The FINFET adder architecture proved to be effective in reducing the propagation delay and leakage power dissipation. This may find usage in high performance devices like microchips and supercomputers. Keywords: Complementary Pass-transistor Logic, Gate Diffusion Input, Low Power Adder, Transmission Gate, CMOS, FINFET

Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders

In this letter, we present a novel methodology to calculate the arithmetic error rate (AER) for deterministic approximate adder architectures, where the calculation of each output bit is restricted to a subset of the input bits, denoted as visibilities . Such architectures have been widely proposed in the literature and are, e.g., obtained when splitting the carry chain in a carry-propagate adder into partitions each computed by a separate parallel adder, or when removing carry-lookahead operators in a parallel prefix adder. Our contribution is a unified calculus for determining the ARE for: 1) such deterministic approximate adder architectures making use of visibilities and 2) the general case of arbitrarily (also nonuniformly) distributed input bits.

Area-Efficient Dual-Mode Fused Floating-Point Three-Term Adder

Floating-point addition is the most frequently used arithmetic operation in almost all general-purpose processors. This paper presents a dual-mode architecture for fused floating-point three-term adder. The traditional architecture for fused floating-point three-term adder is single-mode design where the addition of three operands takes place in a single unit. The existing improved architecture is also a single-mode design that incorporates few optimizations compared to the traditional fused floating-point three-term adder that would reduce area as well as delay. The proposed dual-mode architecture performs either a double-precision addition or two parallel single-precision additions in a single architecture based on the mode selection. The proposed architecture supports both normal and subnormal operations and also exceptional case handling like infinity, NaN and zero cases. The proposed architecture is implemented using both FPGA and ASIC, thus leading to efficient resource sharing, and the area gets reduced compared to two single-precision and a double-precision traditional and improved floating-point adder architectures.

Variable Latency approach in VLSI adder Implemented to Reduce Area and Power

Objective: The Ultimate aim of the VLSI Design is to improve the efficiency, Reduction of Delay and Power Consumption and to minimize the area. In our proposed approach we had implemented the analysis had been done on the field of Speed, Power consumption, Area and Power delay product (PDP) for a carry skip adder with other adders listed as the parallel prefix adders and others. Methods/Statistical Analysis: The Carry-Skip Adder planned here reduces the time required to propagate the carry by skipping over teams of consecutive adder stages, is understood to be comparable in speed to the carry look-ahead technique whereas it uses less logic space and fewer power. Findings: The adders are basic building blocks of the digital circuits for the Signal processing, Integrating and other process of operation. There are various types of adders are proposed in Literature which are commonly used in VLSI Design. The Simulation results also shows that the proposed adder Architecture is Faster and Area efficient compared to other existing adder architecture. Application/ Improvements: They estimate the performance of proposed design will be better in terms of Logic and route delay by experimental results. Keywords: Adders, Carry Bypass Adder (CBA), Carry Increment Adder (CIA), Carry Look-Ahead Adder (CLA), Carry Skip Adder (CSkA), Han Carlson Adder (HCA), Ripple Carry Adder (RCA)

Fast and High-throughput Montgomery Modular Multiplier for RSA Encryption and Decryption

This paper proposes a fast and high-throughput Montgomery modular multiplier that outputs a modular product in binary form. Intermediate operands are kept in carry-save form and added through a two-level, carry-save adder architecture. A carry look-ahead adder is also employed in this multiplier for operand pre-computation and converting the final output from carrysave form to binary form, which accounts for additional clock cycles. The proposed multiplier computes the next two quotients during the iSUPth/SUP iteration to minimize critical path delay, and computes intermediate output for the (i + 2)SUPth/SUP iteration while skipping the (і + 1)SUPth/SUP iteration. In this way, the overall time required for multiplication is minimized significantly, and additional clock cycles required for operand pre-computation and format conversion can be ignored. Experimental results show that the proposed Montgomery modular multiplier can achieve significant speed and throughput improvement, compared to previous designs.