A process-tolerant low-power adder architecture for image processing applications

Bharat Garg,G K Sharma

doi:10.3906/elk-1809-8

Abstract

The aggressive CMOS technology scaling in the sub-100-nm regime leads to highly challenging VLSI design due to the presence of unreliable components. The delay failures in arithmetic units are increasing rapidly due to the increased effect of process variation (PV) in scaled technology. This paper introduces a novel process-tolerant low-power adder (Prot-LA) architecture for error-tolerant applications. The proposed Prot-LA architecture segments the operands into two parts and computes addition of the upper parts in carry-propagate, whereas it computes the lower parts in a carry-free manner. In the Prot-LA, the number of bits in carry-propagate and carry-free additions can be reconfigured based on the amount of PV. An on-chip PV detector is embedded to determine the PV severity. Because of this reconfigurability, the proposed adder completes the carry propagation with minimum error even under severe process variation. The simulation results show that proposed Prot-LA provides 19.9 % reduced power consumption over the state-of-the-art approximate adder. The efficacy of the proposed adder is demonstrated in the real application by designing an image scaling processor (ISP). The simulation results show that the Prot-LA embedded ISP consumes 7.75 % reduced energy with 2.43 dB higher PSNR over the existing approximate adder embedded ISP.

Highlights

The rapid development of the VLSI technology has lead to an exponential growth of portable electronic devices that employ several applications to satisfy user demand
In this paper, we have presented a process-tolerant low-power adder that reduces the large errors occurring due to the process variation by reconfiguring the number of bits in carry-propagate and carry-free paths
The proposed adder reconfigures the number of bits in the carry-propagate path such that large error due to timing failure does not occur

Summary

Introduction

The rapid development of the VLSI technology has lead to an exponential growth of portable electronic devices that employ several applications to satisfy user demand. This paper presents a novel process-tolerant low-power adder architecture that jointly addresses the technology issue and provides improved speed-power-accuracy-area trade-off. Since the RCLA exhibits on two operating modes (accurate/approximate), the design must have more approximate modes with different accuracy-performance trade-off for large applicability All these aforementioned techniques exploit error tolerance of the application and compute the approximate output. The Prot-LA reconfigures the lower adder to compute sum either in carry-propagate (accurate) or in carry-free (approximate) manner based on the value of control signal. As the PV severity increases, the control signal reduces (increases) the number of carry-propagate (carry-free) bits to compute the sum which reduces the large error at MSBs. The subsection details the architecture and working reconfigurable lower part adder i.e. reconfigurable carry-propagate adder

Reconfigurable carry propagation adder: algorithm and architecture

Adders under process variation

ASIC implementation

Findings

Conclusion