RTL Design, Verification and Synthesis of Secure Hash Algorithm to implement on an ASIC Processor

Abstract

In this project we are comparing different architectures and adding the features that increases the efficiency of our architecture. Few of them are including multiplexers in the message digester, using different adder architectures in the required places, reducing the critical path by breaking the longest path and making them to operate parallelly. Use of multiplexers reduces the number of registers required in the message expander. It simply transfers the output of expander to compressor block in every clock cycle. Whenever the number of cycle is greater than 16, the multiplexer switches the select line so that the computed message digest to send as output to the compressor. Using of a carry save adder and adder array takes lesser time to perform addition than a pair of adders array. Finally we all know that reducing the critical path reduces the overall operation time and hence increases the efficiency. Considering all these factors in the design we are designing the microarchitecture for SHA-256 algorithm and obtain the RTL code for that architecture. We have also verified the design by designing a test-bench, and finally synthesized the design.