Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders

Abstract

In this letter, we present a novel methodology to calculate the arithmetic error rate (AER) for deterministic approximate adder architectures, where the calculation of each output bit is restricted to a subset of the input bits, denoted as visibilities . Such architectures have been widely proposed in the literature and are, e.g., obtained when splitting the carry chain in a carry-propagate adder into partitions each computed by a separate parallel adder, or when removing carry-lookahead operators in a parallel prefix adder. Our contribution is a unified calculus for determining the ARE for: 1) such deterministic approximate adder architectures making use of visibilities and 2) the general case of arbitrarily (also nonuniformly) distributed input bits.