Active-matrix Organic Light-emitting Diode Display Research Articles

7‐1: A New a‐IGZO TFT Pixel Circuit for High‐Resolution Mobile AMOLED Display with Highly Stable at Low Gray Levels

This paper proposes a highly stable amorphous indium‐gallium zinc‐oxide (a‐IGZO) thin‐film transistor (TFT) pixel circuit for the active‐matrix organic light‐emitting diode (AMOLED) displays, which can compensate for the non‐uniform threshold voltage (VTH) of the TFT at a low gray level. The stable operation was achieved by minimizing the operation number of the switch connected to the VTH storage capacitor after the VTH compensation stage. The HSPICE simulation verified that the relative current error rate is within only ‐15.7% at 567 pA (13 gray level) against the VTH variations.

P‐5.1: De‐Mura Processing with a High Performance for Low Grayscales in AMOLED Display

Mura artifacts reduction (De‐Mura) processing, with a high performance for low grayscales, is developed and integrated in display drivers for active‐matrix organic light‐emitting diode (AMOLED) display. The proposed De‐Mura processing, designed to compensate an AMOLED panel's luminance Mura (L‐Mura) and color Mura (C‐Mura), shows excellent display performance, and the major display properties include a diminished luminance non‐uniformity under low grayscales (<= Gray 16) and low luminous brightness (<= 2 cd/m 2 ), and an improved visually imperceptible color non‐uniformity. Our works reveals an effective solution to work around the inevitable difficulties of optical measurement of AMOLED panels under low luminous brightness.

Emission Gate Driver With Five Low-Temperature Poly-Si Oxide TFTs Without Capacitor for Narrow-Bezel AMOLED Display

We report a highly simplified emission (EM) gate driver circuit for high resolution and narrow bezel active-matrix organic light emitting diode (AMOLED) display using low-temperature poly-Si oxide (LTPO) thin film transistors (TFTs). The proposed circuit consists of five TFTs, three low-temperature poly-Si (LTPS) and two oxide TFTs. The output signal can be controlled with variable pulse width by starting signal of different pulse width. The fabricated circuit operates well with depletion mode oxide TFTs having threshold voltage of -3.5 V. The output swing from 3 V to -7 V and peak to peak voltage of 10 V were used for the output measurement. The output signals with different duty ratio of 10, 50, and 90% are demonstrated. The power consumption is only 41.5 mW when the duty ratio of EM signal is 90% at refresh rate of 120 Hz for 4k (3840 × 2160) AMOLED display.

Using angle-selective optical film to enhance the light extraction of a thin-film encapsulated 3D reflective pixel for OLED displays.

Light extraction improvement is still an important issue for active-matrix organic light-emitting diode displays (AMOLEDs). In our previous work, a three-dimensional (3D) reflective pixel configuration embedding the OLED in the concave 3D reflector and patterned high-index filler had been proposed for significant enhancement of the pixel light extraction. In this work, influences of thin film encapsulation (TFE) on light extraction of such reflective 3D OLED pixels are considered as well by simulation studies. Unfortunately, the optical simulation reveals strong reduction of the light extraction efficiency induced by TFE layers. As such, an additional angle-selective optical film structure between the pixel and the encapsulation layers is introduced to control the angular distribution of the light coupled into the encapsulation layers and to solve TFE-induced optical losses. As a result, TFE-induced losses can be substantially reduced to retain much of light extraction efficiency. The results of this study are believed to provide useful insights and guides for developing even more efficient and power-saving AMOLEDs.

P‐4.2: De‐Mura Processing Integrated in Display Drivers for AMOLED Display

High‐performance Mura artifact reduction (De‐Mura) processing is developed and integrated in display drivers for raising panel yield. The proposed De‐Mura processing, designed to compensate an active‐matrix organic light‐emitting diode (AMOLED) panel's luminance Mura (L‐Mura) and color Mura (C‐Mura), shows excellent display performance, and the major display properties include a diminished luminance nonuniformity from about 50% to about 10% under different gray levels, and an improved visually imperceptible color nonuniformity. Among 500 pieces of 5.83” (1128×2436, 460 PPI) retina AMOLED panels, panel yield is improved up to 96.8%. Our works reveals an effective external De‐Mura solution integrated in display drivers for panel factories and module suppliers to obtain high panel yield.

Guided-mode resonance in periodic surface textures on Si thin films induced by nanosecond laser irradiation

Laser-crystallization processes to convert amorphous-Si to poly-crystalline-Si are attracted considerable attention owing to their industrial applications, such as in active matrix organic light-emitting diode displays (AMOLEDs) and photovoltaic devices and general scientific interest. Multiple irradiation sequences were conducted with a 355 nm UV laser on amorphous-Si (40, 50, and 60 nm)/oxide(300 nm) layers on glass substrates. The resultant periodic surface textures on Si thin layers were characterized by resonance peaks in the transmittance spectra, depending on the polarization of the normal-incident light. By modeling the periodic textures as 1D linear gratings, the variations in peak intensities and positions were analyzed with respect to Si-layer thickness using the guided-mode resonance theory. In the case of transverse electric polarization, the electric field generated at resonance was entirely concentrated in the Si layer, leading to a red-shift with an increase in Si-layer thickness. Meanwhile, with transverse magnetic polarization, the magnetic field generated at resonance was mainly localized within the Si layer, but was partially distributed in the lower oxide layer when the Si-layer thickness was less than 45 nm and highly concentrated in the Si layer at Si-layer thicknesses greater than 45 nm. These results were consistent with the measured ripple positions and intensities. Thus, we propose that the observed resonance peaks can be used to characterize the surface ripples generated by laser crystallization, for e.g., in optical sensor devices on flexible substrates.

Achieving high sensing in 0.5 nA for the driving pixel currents in AMOLEDs with settling time of 7 µs by a new external current sensing circuit

A new external current sensing circuit with baseline compensation for the active matrix organic light emitting diode (AMOLED) display is developed herein to achieve the sensing precision of 0.5 nA in pixel with 7 µs of settling time. Current sensing circuit incorporates a new push–pull transient current feedforward whereas the current analog to digital converter (CADC) based digital baseline current compensation incorporates an 11-bit current digital-to-analog converter, a current comparator and a digital control circuit with an 11-bit successive approximation register. The proposed integrated mixed signal IC drives a 6T1C pixel-based AMOLED panel with one horizontal time of 7.7 µs at a scan frequency of 60 Hz. The design readout chip can simultaneously sense and compensate TFT baseline current variation. The readout circuit and the baseline compensation circuit are implemented in the integrated chip with chip area of 125 μm × 46 μm and fabricated via TSMC T18 process. With the standard 3.3 V supply, experimental result shows that the overall power consumption of the chip is 988 µW watt. The minimum LSB current for the CADC is 10 nA and the maximum achievable sampling rate is 500 KS/s. The measured INL and DNL of CADC is 0.84 and 0.98 respectively. Despite of heavy data line parasitic capacitances (2.6 KΩ/20 pF) of the AMOLED display, experimental results show that the proposed circuit can sense 0.5 nA current within 7 µs of settling time. The sensing precision of 0.5 nA within 7 µs are the best among all reported literature to date whereas the current sense range (0.5–500 nA), system sampling rate (142 KS/s), INL (0.84) and DNL (0.98) of the CADC is approximately comparable among all reported.

P‐13.13: The Technology of Narrow Border in Mobile Display

Thanks to new display technology development, mobile phone has been evolving from early analog phone to current smart phone. Most noticeable evidences include display evolution from digital to liquid crystal (LCD), and to more recent active‐matrix organic light‐emitting diode (AMOLED), color advancement from monochromic to full‐color, and display panel size from small‐screen to large‐screen. Besides, full‐screen has also become a new trend in mobile phone market since 2017. To meet the full‐screen display and/or to achieve the high screen‐to‐body ratio, display panel makers have come out a variety of screen design, notch, dew‐drop, hole‐punch, etc. Equally important, narrow border is another key technical requirement that will help increase the screen‐to‐body ratio, ultimately, enhancing visual experience. Technically, screen‐to‐body ratio of 90% or higher can be considered as a full‐screen. In order to meet this full‐screen display, it is necessary to reduce the bottom‐border from 4 mm to 1 mm, and leftand right‐borders from 1.2 mm to 0.5 mm, simultaneously. However, narrow border should be compatible with ESD, De‐mux circuits. This would require a width of about 1 mm in the FANOUT area. In addition, since the upper/left/right‐borders are only 0.5 mm or narrower, frit sealing may have only about 300 um in width, putting panel reliability in a great risk.In this paper, we will describe our technology route that not only can meet narrow border specification in the AMOLED display, but also can maintain the panel stability.

P‐189: Distinguished Poster: 3D Pixel Configurations for Optical Out‐coupling of OLED Displays‐ Part I: Optical Simulation

Due to considerations on image quality and fabrication/integration compatibility, current active‐matrix OLED displays (AMOLEDs) hardly adopt any effective light out‐coupling techniques/structures and it remains an unsolved critical technical issue. Recently, through optical simulation, we proposed a 3D pixel configuration as a potential and promising way to boost light out‐coupling of OLED display pixels. With extending the bottom reflective electrode to bank slope of the pixel definition layer (PDL) and selectively filling the bank opening (concave area) with high‐index filler to form the optically reflective concave structure, it is possible to give several‐fold light extraction enhancement. In this paper, we further extend the simulation work by evaluating effects of more realistic graded bank slopes vs. straight bank slope, less challenging non‐patterned (blanket) high‐index filler vs. patterned filler, and real OLED layer stacks and properties. The optical simulation clearly reveals that light extraction enhancement can be mostly kept with more realistic graded bank profiles and even less ideal (but also less challenging) non‐patterned filler can provide substantial extraction enhancement. The graded bank structure also provides beneficial effects on viewing characteristics.

67‐1: Invited Paper: Design of an Advanced Bottom‐emission AMOLED Display for TVs with High‐PPI and Large Size

Top‐gate typed amorphous‐indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film‐transistors (TFTs) and a technologically advanced transparent storage capacitance structure have been successfully employed in pixel circuits. The design procedure was systematically studied. Eventually, a 15‐inch gate‐driver‐on‐array (GOA) drived active matrix organic light‐emitting diode (AMOLED) display was demonstrated with a high resolution of 147 ppi.

Three‐dimensional pixel configurations for optical outcoupling of OLED displays—optical simulation

AbstractBecause of considerations on image quality and fabrication/integration compatibility, current active‐matrix OLED displays (AMOLEDs) hardly adopt any effective light outcoupling techniques/structures, and it remains an unsolved critical technical issue. Recently, through optical simulation, we proposed a three‐dimensional (3D) pixel configuration as a potential and promising way to boost light outcoupling of OLED display pixels. By extending the bottom reflective electrode to bank slope of the pixel definition layer (PDL) and selectively filling the bank opening (concave area) with high‐index filler to form the optically reflective concave structure, it is possible to give several‐fold light extraction enhancement. In this paper, we further extend the simulation work by evaluating effects of more realistic graded bank slopes vs straight bank slope, less challenging nonpatterned (blanket) high‐index filler vs patterned filler, and real OLED layer stacks and properties. The optical simulation clearly reveals that light extraction enhancement can be mostly kept with more realistic graded bank profiles and even less ideal (but also less challenging) nonpatterned filler can provide substantial extraction enhancement. The graded bank structure also provides beneficial effects on viewing characteristics.

Novel Top-Anode OLED/a-IGZO TFTs Pixel Circuit for 8K4K AM-OLEDs

This paper proposes amorphous indium–gallium–zinc oxide thin-film transistors (TFTs) four-transistor-two-capacitor (4T2C) pixel circuit in combination with a top-anode organic light-emitting diode (OLED) for the use in 8K4K active-matrix organic light-emitting diode displays (AM-OLEDs). The proposed pixel circuit compensates for driving TFTs threshold voltage ( ${V} _{\textsf {TH}}$ ) shifts and mobility variations, ${V} _{\textsf {DD}}$ current–resistance ( ${I}$ – ${R}$ ) drops, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ -induced rises. Both the positive and negative ${V} _{\textsf {TH}}$ of the driving TFT can be sensed by the proposed circuit. In this paper, we analyze the impact of the driving TFT compensation time for low gray levels. The current error rates are calculated when TFT mobility variations are considered. The proposed pixel circuit allows an increase in the compensation time to reduce the impact of driving TFT ${V} _{\textsf {TH}}$ and mobility variations on the performance of 4T2C pixel circuit. Conventional two-transistor-one-capacitor, five-transistor-two-capacitor, and proposed 4T2C pixel circuits are simulated and compared in this paper. The proposed pixel 4T2C circuit reduces the current error rates to below 5.79% when the ${V} _{\textsf {TH}}$ shifts of ±2 V, mobility variations of ±10%, ${V} _{\textsf {DD}}~{I}$ – ${R}$ drops of 1 V, and ${V} _{\textsf {SS}}~{I}$ – ${R}$ rises of 1 V are all considered. We show that the proposed 4T2C pixel circuit is suitable for 8K4K AM-OLEDs.

Bottom-Metal Induced Leakage Current of LTPS Diode for ESD Protection

Leakage current behavior was investigated for diode-connected LTPS TFTs (LTPS diode) for electrostatic discharge (ESD) protection in display product with high luminance backlight system. In this study, the bottom metal layer was adopted to suppress leakage current caused by light coming from backlight system. Different off-current behavior as each other electrical connection of metal layer was observed, source-contacted or floating bottom metal showed the high leakage current by increasing current flow through back-channel at off states while gate-contacted bottom metal have comparable low leakage current with non-bottom metal layer. This leakage current characteristic was verified by technology computer-aided design (TCAD) simulation. Objectives and Background A low temperature polycrystalline silicon (LTPS) have been widely used for in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diode displays (AMOLEDs) as thin film transistor (TFT) backplane and system on panel (SOP), combined with controller, memory, and driver circuits, due to excellent electrical characteristics. The LTPS TFT based displays can achieve high brightness, high aperture ratio, high resolution, and low power consumption due to excellent electrical characteristics. On the other hand, in display product with high luminance backlight system, such as auto and mobile products, the LTPS TFTs require a bottom metal layer to reduce leakage current caused by light coming from backlight unit (BLU). This bottom metal layer in contacted with gate or source electrodes is applied under the poly-Si layer. However, this bottom metal layer may also affect seriously the leakage current of diode-connected LTPS TFTs (LTPS diode) for electrostatic discharge (ESD) protection in SOP. In this study, the leakage current of LTPS diode for ESD protection was investigated with gate-contacted bottom metal, source-contacted bottom metal, and floating bottom metal compared with non-bottom metal. We measured the electrical characteristics with variation of electrical connection of bottom metal layer. Also, the technology computer-aided design (TCAD) simulation was performed to analyze the physical mechanism. From analysis results, optimized bottom metal design of LTPS diode was proposed for ESD production. Experiment Figure 1 shows the top-gate coplanar n-channel LTPS TFT structure with bottom metal layer under poly-Si. Gate and Drain electrodes were connected to common electrode in LTPS TFTs structure for LTPS diode. This LTPS diode was fabricated at low temperature of less than 450°C on glass substrate. The standard commercial NMOS processes, including the ion implantation, the excimer laser annealing (ELA), and the rapid thermal annealing (RTA), were employed in this experiment. To observe the electrical characteristics of LTPS diode, I-V characteristics were measured by using an Agilent B1500A semiconductor analyzer at room temperature. Results and Discussion Figure 2 shows I-V characteristics of LTPS diodes with gate-contacted bottom metal, source-contacted bottom metal, and floating bottom metal compared with non-bottom metal. The leakage current with source-contacted and floating bottom metal increased considerably compared with non-bottom metal. Especially, the leakage current with source-contacted bottom metal increased more than with floating bottom metal. On the other hand, the leakage current with gate-contacted bottom metal was low enough to be comparable with non-bottom metal. To analyze this phenomenon, we observed the electron concentration distribution within poly-Si at VGS= 0V, 10V, and -10V region using technology computer-aided design (TCAD) simulation as shown figure 3. For source-contacted bottom metal and floating bottom metal, at VGS= -10V, the electron was accumulated in the back-channel of poly-Si since the positive voltage is applied to back-channel by voltage difference between drain and bottom metal even though drain (=gate) electrode is applied to negative voltage. Therefore, at VGS= -10V, the leakage current flows through the back-channel in LTPS diodes with source-contacted bottom metal and floating bottom metal. But, for LTPS diode with gate-contacted bottom metal, when drain electrode was applied to negative voltage, there is no different voltage bottom metal and gate electrode because these electrodes were linked in common. Therefore, LTPS diode with gate-contacted bottom metal has low leakage current as comparable with non-bottom metal. Conclusion In summary, the leakage current of LTPS diode was strongly dependent on electrical connection of bottom metal layer. The electrical connection of bottom metal affects back-channel region within poly-Si due to the difference between bottom metal and drain electrodes at off region. Especially, LTPS diode with source-contacted bottom metal and floating bottom metal increased considerably the leakage current, while, gate-contacted bottom metal decreased leakage current. Therefore, bottom metal layer should be connected by gate electrode in LTPS diode for ESD protection. Figure 1

High-Accurate and Fast Power Model Based on Channel Dependency for Mobile AMOLED Displays

Recently, active matrix organic light-emitting diode (AMOLED) displays have widely been used for user-interface applications on smartphones. Since frequent interactions between a user and a display which come from such applications tend to incur big display power consumption, the display power efficiency should be managed exactly and fast. For this purpose, a high-accurate and fast power model for AMOLED displays is greatly required for efficient power management. In this paper, we propose a novel high-accurate and fast power model for AMOLED displays, which is developed using a multiple regression technique to account for the dependency between R, G, and B channels and is polished using various performance optimization techniques. Then, the proposed model is applied to five AMOLED display panels of a CHIMEI panel and Galaxy S1, 3, 5, and 7 panels from SAMSUMG. The average error rates are obtained on these panels for four well-known image datasets. The proposed model shows the lowest error rate of 1.29% on Galaxy S7, while the simple model and Park’s model show the error rates of 6.91% and 6.57%, respectively. In addition, in order to guarantee the fast execution time of the proposed power model on smartphones, we implement performance optimizations to the model. For runtime application, the proposed power model is implemented at the operating system level of the Android smartphone equipped with Exynos 4412. The optimized power model shows an average execution time of approximately 7.77 milli-seconds per image displayed on the panel with 720x1280 resolution. Consequently, the proposed power model is shown to be very fast and accurate, and thus it is highly useful in smartphones with AMOLED displays.

Contrast‐aware power control method for mobile active‐matrix organic light‐emitting diode display

Mobile display technology has been developed fast and low-power design for the display is more important than ever. Hardware techniques for low-power design are not flexible and the existing software techniques are not considering the characteristics of the display panels. In this study, a histogram-based contrast-aware power control method for active-matrix organic light-emitting diode display is proposed. The proposed power control method solves an optimisation problem to achieve power control with maximum contrast available. A new histogram representation is also proposed to calculate the power consumption of an image efficiently in the optimisation process. Simulation results and hardware experiment results show that the proposed method provides both precise power control and better contrast of the output image.

OPT: optimal human visual system-aware and power-saving color transformation for mobile AMOLED displays

Organic light-emitting diode (OLED) displays have a high power efficiency; however, the frequent use of user interaction-based applications such as instant messengers, video players, and games contributes strongly to the total power consumption. The power consumption varies significantly depending on the display contents, and thus, color transformation, which is a representative low-power technique, is used for OLED displays. Previously developed low-power color transformation methods have not been thoroughly researched for satisfying the human visual system and have not considered optimal visual satisfaction and power consumption simultaneously. In this paper, a novel low-power color transformation approach is proposed, which is aimed at simultaneously optimizing both visual satisfaction and power consumption. In addition, it is implemented on an active-matrix OLED (AMOLED) display-based Android smartphone at runtime. Experimental results show that the proposed technique achieves better human visual satisfaction and shows up to 22.32% power saving on average on the AMOLED display and offers 6.23% more extended battery life over that of an existing leading technique.

Tunneling contact IGZO TFTs with reduced saturation voltages

We report a tunneling contact indium-gallium-zinc oxide (IGZO) thin film transistor (TFT) with a graphene interlayer technique in this paper. A Schottky junction is realized between a metal and IGZO with a graphene interlayer, leading to a quantum tunneling of the TFT transport in saturation regions. This tunneling contact enables a significant reduction in the saturation drain voltage Vdsat compared to that of the thermionic emission TFTs, which is usually equal to the gate voltage minus their threshold voltages. Measured temperature independences of the subthreshold swing confirm a transition from the thermionic emission to quantum tunneling transports depending on the gate bias voltages in the proposed device. The tunneling contact TFTs with the graphene interlayer have implications to reduce the power consumptions of certain applications such as the active matrix OLED display.

9.1‐inch stretchable AMOLED display based on LTPS technology

AbstractIn this work, we report a freeform shaped active‐matrix organic light‐emitting diode (AMOLED) display based on low‐temperature polycrystalline silicon technology. It was found that our AMOLED, developed with a unique pixel structure, can withstand in various desired shapes featuring its stretchable property with no degradation of image quality and device characteristics. We demonstrated unprecedented convex/concave shape of the 9.1‐inch AMOLED display by low‐temperature thermoforming process. The AMOLED display with freeform design is promising for future display applications such as automotive, Internet of things devices, and wearable electronics.

Shaping the Spatial and Temporal Noise Characteristics of Driving Signals for Driving AMOLED Display

In this paper, a digital driving technique for generating binary driving signals to display a digital video on an active-matrix organic light-emitting diode (AMOLED) panel is proposed. The ideal spatial and temporal noise characteristics of the driving signal for an AMOLED panel to display high-quality video are first suggested. Based on the suggested characteristics, a digital driving technique is proposed to generate the driving signals for an AMOLED panel. Simulation results show that the proposed driving technique can generate driving signals having the desired spatial and temporal noise characteristics and, accordingly, allows an AMOLED panel to display video of better quality than other conventional driving techniques in terms of various measures.

Influence of Passivation Layers on Characteristics of High Mobility Amorphous Indium-Zinc-Tin-Oxide Thin-Film Transistors

Amorphous oxide semiconductors (AOS) have recently attracted much attention as potential channel layer in thin film transistors (TFTs) due to high carrier mobility, transparency in visible light and room-temperature deposition. Among various materials, the TFTs based on amorphous Indium Gallium Zinc Oxide (a-IGZO) are expected to be a promising technology for the next generation novel flat panel display development [1], in particular for high resolution Liquid Cristal Display (LCD) [2]. The average field-effect mobility of TFT with sputter-deposited a-IGZO thin film as a channel layer is around 10 cm2/Vs and it’s not high enough (20 cm2/Vs) for future display applications such as ultra-high definition (UHD) display, active matrix organic light-emitting diode displays (AMOLEDs) and system driving circuits integrated with the TFT array process [3, 4]. Compared with other amorphous oxide semiconductor materials, amorphous indium-zinc-tin oxide (a-IZTO) is promising candidate for achieving high mobility oxide TFTs [5, 6]. Although the properties of oxide semiconductor films can be easily controlled by radio-frequency (RF) sputtering, the subsequent processes, particularly the passivation layer growth, often cause destructive impacts on channel layer [7]. The challenge in fabricating high performance a-IZTO TFTs actually lies in the post processes rather than in the a-IZTO film deposition. Therefore, it is necessary to investigate the effect of the passivation layers on the characteristics of a-IZTO TFTs. In this study, we investigated the effect of the plasma enhanced chemical vapor deposition (PECVD) deposited passivation layer (SiO2) on the characteristics of a-IZTO TFTs. The threshold voltage (Vth ) of the TFTs was found to be highly dependent on the deposition condition of passivation layer, which is ascribed to ion bombardment induced by PECVD process. By adjusting the post annealing temperature, the Vth of the TFTs can be well controlled to the desired range. We investigated the influence of passivation-layer deposition on the characteristics of a-InZnSnO thin-film transistors (TFTs). The threshold voltage (Vth ) of the TFTs shifted markedly as a result of the ion bombardment induced by the passivation layers above. By adjusting the post annealing temperature, the performance of the TFTs can be modulated. The a-InZnSnO TFTs after passivation exhibited good performance with a field-effect mobility of 21.34 cm2 /Vs, a threshold voltage of -5.03V, and a subthreshold slope of 0.52 V/decade. Reference [1] M. A. Marrs, C. D. Moyer, E. J. Bawolek, et al., " Control of Threshold Voltage and Saturation Mobility Using Dual-Active-Layer Device Based on Amorphous Mixed Metal–Oxide–Semiconductor on Flexible Plastic Substrates," IEEE Transactions on Electron Devices, vol. 58, pp. 3428-3434, 2011. [2] T. Kamiya, K. Nomura, and H. Hosono, “Present status of amorphous In-Ga-Zn-O thin-film transistors,” Sci. Technol. Adv. Mater., vol. 11, no. 4, Aug. 2010, Art ID 044305. [3] J. U. Bae, D. H. Kim, K. Kim, K. Jung, W. Shin, I. Kang and S. Yeo, “Development of oxide TFT’s structures,” in SID Symp. Dig., Jun. 2013, vol. 44, no. 1, pp. 89–92. [4] L.F. Teng, P.T. Liu, Y.J. Lo, and Y.J. Lee, “Effects of microwave annealing on electrical enhancement of amorphous oxide semiconductor thin film transistor,” Appl. Phys. Lett., vol. 101, no. 13, p. 132901, Sep. 2012. [5] K. Jang, J. Raja, Y.J. Lee, D. Kim, and J. Yi, “Effects of carrier concentration, indium content, and crystallinity on the electrical properties of indium-tin-zinc-oxide thin-film transistors,” IEEE Electron Device Lett., vol. 34, no. 9, pp. 1151–1153, Sep. 2013. [6] N. Morosawa et al., “High-mobility self-aligned top-gate oxide TFT for high-resolution AM-OLED,” in SID Symp. Dig., Jun. 2013, vol. 44, no. 1, pp. 85–88. [7] T. T. T. Nguyen, B. Aventurier, T. Terlier, J. P. Barnes, and F. Templier, “Impact of Passivation Conditions on Characteristics of Bottom-Gate IGZO Thin-Film Transistors,” J. Display Technol., vol. 11, no. 6, pp. 554–558, June. 2015