65nm Technology Research Articles

Design Of A Phase-Locked Loop Using Current Starved Voltage Controlled Ring Oscillator In 45nm Technology

Design Of A Phase-Locked Loop Using Current Starved Voltage Controlled Ring Oscillator In 45nm Technology

Performance Analysis of 8x4 Barrel Shifters in CMOS and FINFET Technology

Shifters are essential components in digital circuits, enabling data manipulation and routing for a wide range of computational tasks. This study presents a comprehensive performance analysis of 8x4 barrel shifters implemented in two distinct semiconductor technologies: Complementary Metal-Oxide-Semiconductor (CMOS) and FinFET. This study compares and evaluates the important parameters for these shifters at both technological nodes, such as power consumption. Additionally, we examine the effects of scaling on CMOS barrel shifters. Conversely, FinFET technology, recognized for overcoming certain limitations of CMOS, is assessed for its potential to enhance performance while preserving energy efficiency. Through detailed simulation and analysis, this study offers valuable insights into the benefits and limitations of CMOS and FinFET implementations for 8x4 barrel shifters. The circuit is implemented using Cadence Virtuoso and optimized to leverage the unique features and address the limitations of 45nm CMOS and 22nm FinFET technologies. Furthermore, the study offers recommendations for selecting the appropriate technology based on specific performance criteria and application needs. The findings aim to guide future design decisions and improvements in shifter technology.

Decoder and Multiplexer Comparison with Mixed Logic and CMOS Logic with 90nm Technology

Decoder and Multiplexer Comparison with Mixed Logic and CMOS Logic with 90nm Technology

The single event upset hardened design of spin transfer torque magnetic random access memory read circuits at 40 nm technology

With the advancement of technology nodes, the challenging space radiation environment poses a significant threat to memory reliability. Spin transfer torque magnetic random access memory (STT-MRAM) is a formidable candidate for non-volatile memory for space applications due to its advantages of non-volatility, durability, speed and compatibility with CMOS technology. Although the STT-MRAM memory unit magnetic tunnel junction (MTJ) is naturally immune to radiation effects, the single event upset (SEU) affects the peripheral circuitry. A radiation-hardened circuit is proposed, which theoretically does not have ‘0' upset nodes and automatically recovers from ‘1' upset. Moreover, the circuit's radiation-hardened performance was corroborated through hybrid simulation utilizing 40-nm technology. The findings of this investigation hold significance for the use of space radiation-hardened STT-MRAM.

Design of 8T DTMOS Schmitt Trigger SRAM Cell for IOT Applications

Abstract Internet of things (IoT) based systems require power-efficient circuits to raise the battery lifeline. This study presents a single-ended 8T SRAM cell. The core of the proposed 8T SRAM cell is composed of a Schmitt-Trigger circuit which a dynamic body bias technique is applied to a standard CMOS inverter through a feedback mechanism, whereby the threshold voltages of two MOSFETs can be changed, thus changing the switching voltage. Read operation of the proposed cell is conducted using the shared footer per word transistor. The write path is cut-off during the read operation, improving RSNM. A transmission gate placed in the cell core is used to cut the feedback path during write operation. To prove superiority of the proposed cell it is compared with four state-of-the-art SRAM cells under identical conditions on Cadence Virtuoso using 45nm technology at VDD=0.8 V. The proposed circuit shows a 135.74 % improvement in terms of RSNM and a 44.04 % improvement in terms of peak-to-peak power compared to the 6T DTMOS Cell.

A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator

This paper presents a 10-bit 60-MS/s SAR ADC using an energy-efficient common-mode variation suppression (CMVS) switching scheme. The proposed CMVS switching scheme reduces energy consumption by about 92 % compared to the conventional scheme. Also, it narrows the common-mode variation to 16.6 % VDD. It improves the accuracy of the SAR ADC and makes the comparator and SAR ADC operate at the best-performance region. The proposed comparator adopts a gain boosting dynamic capacitive pre-amplifier to enhance the amplification and accelerate the comparison speed. The regeneration latch keeps the cross-coupled inverter structure to ensure high-speed regeneration. The input pair of the latch suppresses the through current while decreasing the regeneration speed. Therefore, an auxiliary input pair is added to enhance the regeneration speed. The SAR ADC is designed and simulated using 65-nm Cryo-CMOS technology with VDD = 1.2 V. At T = 300 K, it achieves a FoM of 15.39 fJ/conversion-step with 55-MS/s. At T = 4 K, it achieves a FoM of 14.15 fJ/conversion-step with 60-MS/s.

Issues and Challenges in Small-Signal Low-Power Amplifiers: A Review

Background: Contemporary linear electronic circuit designs frequently include small-signal low-power amplifiers as a fundamental building block. These amplifiers are widely used as LNAs (Low Noise Amplifiers) in the pre-amplifier stages of both low-frequency and high-frequency featured electronic circuits. Objectives: To review the recent advances in the design of small-signal low-power amplifiers based on device configuration of BJTs, JFETs and MOSFETs for low (≤1KHz) and high frequencies (≥1MHz) at smaller input voltage (<1 Volt). Methods: The articles published between 2010 to 2024 are shortlisted from IEEE Xplore, Springer, Science Direct Elsevier, Google Scholar, and MDPI databases and the outcomes of the different techniques are compared on various parameters. Findings: It is found that four-stage CMOS amplifier at TSMC 40nm process technology emerges with highest 84.59dB gain, InP (Indium Phosphide) Distributed Amplifier Using 3-D Interdigital Capacitors carries widest bandwidth of 160 GHz, two stage darlington pair amplifier at 0.18μm under dual input and dual output topologies and four stage CMOS amplifier at 40nm technology realizes lower power consumption of 0.5mW and 0.00086 mW respectively. Small Signal Amplifier based on single stage BJT-JFET Sziklai pair operates at lowest frequency of 11.36 Hz, single stage LNA at 180nm CMOS technology using inductive degenerate topology works at very low supply voltage at +0.5V and, recently reported complementary sziklai based small signal amplifier under CC mode works at lowest -15V supply voltage. Novelty: The review proposed on ‘Small Signal Low Power Amplifier’ is first time reported in this paper. Moreover, it discusses low power small signal amplifiers at both low (≤1KHz) and high (≥MHz) frequencies considering gain enhancement technique, power dissipation reduction technique, and noise reduction technique whereas other review papers emphasize on the general discussion of different topologies only at high frequencies. Keywords: Small-Signal Amplifiers, Low Power Amplifiers, BJTs, JFETs, MOSFETs

A Novel Sinusoidal Oscillator Using Single Voltage Differencing Buffered Amplifier

In this paper, a voltage differencing buffered amplifier (VDBA)-based second-order sinusoidal oscillator (SO) configuration, which provides voltage output at low impedance, is proposed. The circuit employs single VDBA, three resistors and two grounded capacitors, which presume its easy monolithic integration with preferred circuit simplicity. The nonidealities of VDBA due to parasitic and tracking errors are taken into consideration to study the nonideal behavior of proposed SO. Mathematical modeling of phase noise is computed in the paper. Active and passive sensitivities are calculated for the proposed configuration and are found to be less than unity rendering circuit insensitive to component variations followed by phase noise study. The functionality of the proposed topology is validated through cadence virtuoso ADE spectre tool at 180-nm technology node. Experimental verification is executed through commercially available ICs AD844 by good results. The total harmonic distortion (THD) is found to be below 3.5%. The observed frequency of oscillation is found to be in close agreement with the theoretical values. The PVT and Monte Carlo statistical analyses are also carried out to confirm the sensitivity of the proposed SO.

An exponential variation based PSO for analog circuit sizing in constrained environment

This work presents an Exponential Variation based Particle Swarm Optimization (EV-PSO) algorithm to improve the convergence rate and find an optimal solution to analog circuit optimization problems in a constrained-driven environment. Existing evolutionary algorithms have a lower convergence rate leading to higher design time. This work introduces two novel parameters, ζ1 and ζ2, into the velocity update equation. These parameters dynamically vary with the number of iterations. The algorithm was implemented on the Python platform. The results have shown that, in comparison to the considered existing methods, the exponential variation of the parameters ζ1 and ζ2 in the proposed algorithms have a larger rate of convergence. The proposed EV-PSO has a convergence rate of 27 iterations, which is 57.8%, 65.38%, and 59.1% better than the conventional PSO, differential evolution (DE) and genetic algorithm (GA) respectively. The typical design obtained from the optimal solution is verified through the simulation using 45-nm CMOS technology. The optimal solution presented in this work meets the desired input specifications within the specified constrained environment.

Structure and Principles of Operation of a Quaternion VLSI Multiplier

The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using 130nm technology. The developed scripts in VHDL are available in the GitHub repository.

Static Characterization of A Proposed Noise Immune Sram Cell at the 16nm Technology Node

Static Characterization of A Proposed Noise Immune Sram Cell at the 16nm Technology Node

Design of a Radiation-Hardened SRAM Cell using 16nm Technology Node

Electronic circuits are exposed to very high energy radiation in the harsh conditions of outer space. This leads to soft errors such as single-event upsets (SEU), double-event upsets (DEU) and single-event transients (SET). The memory circuits are the most susceptible to these soft errors resulting in severe data loss. This paper proposes the design for an SRAM cell that is radiation hardened by design (RHBD). A comparative study of the standard SRAM cell and the RHBD SRAM cell indicates that the proposed design is resilient to SEUs and DEUs. The proposed design is an improvement on the 8T SRAM cell design and includes a 20T triple interlocked cell (TICE) design. The error correction capabilities of both designs are compared by manually injecting bit upsets at crucial nodes in the circuit. It is observed that the TICE design provides a 96.75% and 98.5% improvement over the standard 8T cell for 1-0 and 0-1 bit upsets respectively. The proposed design has been implemented using the 16nm model from the Arizona State University’s Predictive Technology Model (ASU-PTM), and the LTSpice software was used to carry out the simulations. Tools used: LTSpice v17 is the tool used to design the schematic circuits and to obtain the simulation results. The library file used to design the schematic is the 16nm technology node from the library of the Arizona State University’s Predictive Technology Model (ASU-PTM). Methods: To perform a comparative study of the 8T SRAM and 20T TICE, the schematic circuits were designed using the 16nm technology node in LTSpice. A baseline for the expected voltages of logic 0 and logic 1 is established before injecting errors at the sensitive voltage nodes of the circuit. The next step is to manually inject bit upsets at the crucial nodes of the memory cell to induce either a 0-1 upset or a 1-0 upset. The read/write operation is carried out along with the error injection to compare the error mitigation capacity of the circuits. Finally, the results are tabulated to prove that the 20T TICE is resilient to soft errors arising from exposure to high radiation. Results: During the normal operation of the 8T SRAM cell, the observed output voltage corresponding to logic 0 and logic 1 are 25mV and 780mV respectively. The voltage levels increased to 400mV during a 0-1 upset and dropped to 25mV during a 0-1 bit upset. This indicates that the cell is not reliable. In case of the 20T RHBD cell, the voltage levels for the normal operation were 5mV (logic 0) and 780mV (logic 1). The major improvement is shown in the case where the 20T TICE is injected with bit upsets, since it delivers a voltage of just 6mV during a 0-1 bit upset and maintains a voltage of 770mV during a 1-0 bit upset. Conclusion: The work performs the schematic designs for the comparison of the error mitigation capabilities of a 8T SRAM cell and a 20T TICE which is radiation hardened by design. The study proves that the 20T cell is capable of successfully mitigating both a 1-0 bit upset and a 0-1 bit upset

CNTFET-Based Single-Ended Fractional Order Colpitts Oscillator: Design, Simulation and Comparative Analysis

In this paper, we design and simulate a Single-Ended Colpitts Oscillator (CO) in integer and fractional order domains. The oscillators are realized in 32[Formula: see text]nm node conventional MOSFET and carbon nanotube field effect transistor (CNTFET) technologies. Therefore, four COs have been designed, simulated and rigorously compared. These include integer order conventional MOSFET-based CO, fractional order MOSFET-based CO, CNTFET-based integer order CO and CNTFET-based fractional order CO, all based on 32-nm technology nodes. The fractional order approach has been used as it results in better control over the phase and frequency of the oscillator. Herein, fractional order capacitors of various orders, used in realizing the fractional order COs, are realized and their frequency responses are studied. This is being done to ensure whether the designed pseudo-capacitances have fractional behavior or not in the desired frequency and phase spectrum. It has been observed that the variation of fractional order [Formula: see text] from 0.4 to 0.81 has resulted in a slight reduction of oscillation frequency from 1.68[Formula: see text]GHz ([Formula: see text]) to 1.351[Formula: see text]GHz ([Formula: see text]) keeping the pseudo-capacitance same at 0.3[Formula: see text]nF in MOS-based topology. Since the fractional order realization increases the circuit complexity and power consumption, therefore, CNTFET-based integer order as well as fractional order COs have been designed. The CNTFET-based fractional order CO retains the advantages of the fractional order domain as well as the power efficiency of CNTFETs. Further, it has been observed that integrating fractional-order capacitor (FOC) with the CNTFET CO results in a much larger constant phase zone (CPZ), an important performance measuring parameter. A rigorous comparative analysis of the four COs designed in this work has been performed.

A power-efficient fast-transient OCL-LDO with adaptive super source follower and active capacitor compensation management

This paper presents a flipped voltage follower (FVF) based output-capacitor-less low-dropout regulator (OCL-LDO) with fast transient response, high power supply rejection (PSR), and low quiescent current for noise-sensitive circuits in internet-of-things (IoTs). An adaptive super source follower (ASSF) is proposed to effectively reduce the output impedance of the voltage buffer under heavy-loading conditions while keeping a low quiescent current under light-loading conditions. The active capacitor compensation management (ACCM) is proposed to solve the charge-sharing problem caused by the floating capacitors in the dynamic capacitor compensation circuit. The proposed OCL-LDO has been designed and fabricated in 22-nm CMOS technology. It can stabilize with load current ranging from 0 to 12 mA while consuming only 4.8-μA quiescent current. when the load current steps from 0.1 to 10 mA within 3.8 ns, the measured voltage undershoot is 55 mV and the recovery time is about 60 ns.

Novel machine learning-driven optimizing decoding solutions for FPGA-based time-to-digital converters

Calibration of models and data structures is recurring in a large number of cross-cutting applications from finance to engineering. Even though there are numerous and well-established specific calibration techniques for each application sector, using Neural Networks (NNs) can improve performance. For instance, Tapped Delay-Line Time-to-Digital Converters (TDL-TDCs) implemented in Field Programmable Gate Arrays (FPGAs) are increasingly being used in a variety of research applications, such in the time-resolved spectroscopy or in medical imaging mainly for their high-precision and flexibility. Specific decoding on the sampled information from the TDL, together with calibration to compensate for non-idealities, (i.e., Bubble Errors, BEs, and Process–Voltage–Temperature fluctuations, PVTs) are carried out for generating the conversion of digital codes to time units. In this fundamental process, the impact of Machine Learning (ML) usage has not yet been investigated. In this paper, focusing on advanced FPGA devices (i.e., 28-nm, 20-nm, and 16-nm), we propose an approach based on NNs running in Python on a standalone PC to identify the optimal conversion from digital codes to timestamps, comparing it with the classical fully FPGA-based solution c literature. The experimental validations are performed on Artix-7 (XC7A100TFG256-2) and Kintex UltraScale (XCKU040-FFVA1156-2-E) in 28-nm and 20-nm technology nodes, achieving precision of 12.9 ps r.m.s. and 4.85 ps r.m.s., respectively. These results are in line with the state-of-the-art, demonstrating that in 28-nm technology, the bubble compression algorithm is sufficient to achieve high-precision, while reordering mechanism is crucial to compensate for BEs within the 16/20-nm technology node.

ANN-based framework for modeling process induced variation using BSIM-CMG unified model

In this work, we present a machine-learning augmented compact modeling framework for modeling process induced variations in advanced semiconductor devices. The framework employs BSIM-CMG unified compact model at the core and can be used for any advanced devices like GAA nanosheets and nanowires, FinFETs etc. We have validated the model with extensive numerical simulations and experimental data such as 14nm technology FinFET and 24nm technology Nanowire. Our results show excellent accuracy in modeling variability in key electrical parameters of the device including off-current (Ioff), on-current (Ion), threshold voltage (Vth), subthreshold swing (SS) etc. We observe that the overall accuracy of the ML-based framework strongly depends on the nature and physical behavior of the core model used for modeling the nominal device.

A Low Power PLL with 1-V Supply Voltage and Two-Stage Ring Oscillator in 180-nm CMOS

This paper proposes a low-power charge pump PLL (CPPLL) with 1-V supply voltage in 180-nm CMOS technology, which serves as a low-cost clock generator for heterogeneous integration. Tradeoffs between power consumption, jitter performance and limited loop bandwidth in the conventional CPPLL have been analyzed first, followed by the explanations on reference spur issues in wide bandwidth architectures. A novel two-stage ring oscillator with low voltage capability and linear control gain has been proposed and analyzed in detail, which facilitates the implementation of this 1-V design. Fabricated in SMIC 180-nm technology, the designed PLL occupies a die area of 0.177[Formula: see text]mm2 with an integrated loop filter. The PLL draws 1.8[Formula: see text]mA when working at 480[Formula: see text]MHz, and shows a rms jitter of 7.2[Formula: see text]pS, which is 20 times more power efficient compared with PLLs with similar frequency and technology node. The design shows potential for heterogeneous integration.

High-performance anti-series diode ring amplifier for switched capacitor circuits

Ring amplifiers enable efficient amplification with less power consumption. These are characterized by fairly power requirements, and innate rail-to-rail output swing and are robust against PVT variations. In this paper, we are presenting an improved self-biased anti-series diode-based ring amplifier (ASD-RAMP) design, implemented on 45-nm CMOS technology. The design uses two diode-connected PMOS transistors that are connected in an anti-series manner to generate a large resistance because of which a high dead-zone voltage is generated. The ASD-RAMP has a settling time of only 4.05 ns, which is nearly half of the conventional self-biased ring amplifier (CSB-RAMP). In comparison to CSB-RAMP, the proposed ASD-RAMP improves the dead-zone voltage by 1.1× while requiring 6.76% less power. The circuit is durable and suitable for high-performance applications since it exhibits great resilience to PVT variations in addition to the improved dead zone voltage and reduced settling time.

Innovative techniques for achieving flat response in a dual-resonance ultra-wideband low-noise amplifier

This paper introduces a two-stage ultra-wideband low-noise amplifier (UWB-LNA) intended to be used in wireless communication systems. The architecture uses a novel double-resonance load network in the first stage and resistive shunt feedback in the second stage to achieve wide bandwidth with a flat response. A common gate stage at the input port seeks to present a high-impedance load to the single resonant network, while concurrently shunt negative feedback, source degeneration, and cascoded feedback schemes are used to improve performance. In this respect, the cascoded feedback provides flat gain across a wide bandwidth, while the source degeneration helps in impedance matching. Post-layout foot-print for the UWB-LNA designed and simulated using Cadence Virtuoso 180nm technology is 0.532 mm2 with an operating frequency 3.1–10.6 GHz incorporated. Operating on a 1.8 V supply voltage, it consumes 6 mW of power. The amplifier achieves a maximum gain of 18.75 dB, maintaining a flat low noise figure of 3.15 dB across frequencies ranging from 3.1 to 10.6 GHz. Stability analysis using the Roulettes test confirms the reliability of the proposed LNA, with Kf > 1 and Δ < 1.

A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology

—A 64Gbps 4-level pulse amplitude modulation (PAM4) mixed-signal receiver incorporating a decision-feedback equalizer (DFE) for application in wireline communication is implemented in fully-depleted silicon-on-insulator (FDSOI) 22nm technology. A two-stage slicer with body biasing is proposed to alleviate the stringent timing constraint of the closed-loop DFE. The smaller loading of the first stage shortens the output delay so as to provide a much larger differential input for the second stage. Moreover, body biasing is applied to the proposed slicer to allow higher drive and faster switching capabilities. Simulation results demonstrate that the receiver with body biased two-stage slicer achieves at least 9.9 % and 14.3 % improvements in recovered eye height and eye width over the receiver with StrongArm slicer. The receiver consumes a power of 117.1mW, achieving 1.83pJ/bit energy efficiency.