A Low Power PLL with 1-V Supply Voltage and Two-Stage Ring Oscillator in 180-nm CMOS

Abstract

This paper proposes a low-power charge pump PLL (CPPLL) with 1-V supply voltage in 180-nm CMOS technology, which serves as a low-cost clock generator for heterogeneous integration. Tradeoffs between power consumption, jitter performance and limited loop bandwidth in the conventional CPPLL have been analyzed first, followed by the explanations on reference spur issues in wide bandwidth architectures. A novel two-stage ring oscillator with low voltage capability and linear control gain has been proposed and analyzed in detail, which facilitates the implementation of this 1-V design. Fabricated in SMIC 180-nm technology, the designed PLL occupies a die area of 0.177[Formula: see text]mm2 with an integrated loop filter. The PLL draws 1.8[Formula: see text]mA when working at 480[Formula: see text]MHz, and shows a rms jitter of 7.2[Formula: see text]pS, which is 20 times more power efficient compared with PLLs with similar frequency and technology node. The design shows potential for heterogeneous integration.