6T SRAM Cell Research Articles

Design and Analysis of XNOR-SRAM for In-Memory Computing

Abstract: The use of in-memory computing is a promising strategy with the potential to circumvent the von Neumann bottleneck and improve the overall performance of contemporary computer systems. In this study, the design and analysis of an innovative XNOR-SRAM cell for use in in-memory computing applications is presented. The performance of the suggested cell is assessed using crucial parameters such as cell ratio (CR), pull-up ratio (PR), static noise margin (SNM), write margin (WM), and read margin(RM)MA. Simulation and optimization of the proposed cell are carried out with the assistance of LTSPICE and the HSPICE tool . According to the findings, the XNOR-SRAM cell has greater performance when compared to the traditional 6T SRAM cell. This paves the way for the XNOR-SRAM cell to become a viable choice for in-memory computing.

Transmission Gate Based 8T SRAM Cell for Biomedical Applications

Abstract: There is an immense necessity for several kB of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMS dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Biomedical applications eliminating the use of peripheral circuitry during the read operation. This topology offers a smaller area, reduced delay, low power consumption, and improved data stability in the read operation. Static Random Access Memories mostly contribute to the performance, area, and power dissipation of digitally integrated systems. The mentioned implantable and wireless applications require low-power circuits operating for a long time, occupying less area without degrading the performance, as it provides inconvenience and may even be risky especially while considering the implantable devices.

A 7T high stable and low power SRAM cell design using QG-SNS FinFET

System on Chip (SoC) low power cache memories are in great demand. This requires novel devices like FinFET instead of MOSFET. FinFET comes out as a multi-gate, non-planar device which controls the short channel effects, power dissipation and leakage current. 7T SRAM cell designed using the Quad Gate Stacked Nano-sheets (QG-SNS) FinFET device has been presented. The simulation methodology and the performance parameters of QG-SNS FinFET device have also been discussed. The device shows better ON current, reduced leakage current and improved subthreshold slope. The performance of the 7T SRAM cell designed using QG-SNS FinFET (7T_SNS) for read-write operation has been analyzed in regard to leakage power, propagation delay and stability. This work compares the performance of 7T_SNS SRAM cell with other SRAM cells at nano-scaled technologies. The 7T_SNS SRAM cell achieves 370% better read stability compared to 6T CMOS cell. Write static noise margin of 7T_SNS cell is almost like 6T CMOS SRAM. The leakage power and read power of 7T_SNS cell is 99.99% better as compared to 6T CMOS SRAM. Therefore, a 7T_SNS SRAM cell design having minimum power utilization and better read stability is discussed in this paper.

Accurate Estimation of Data Retention Voltage (DRV) for a 6T SRAM Cell at 45 nm, 65 nm, and 130 nm Technology Nodes

Scaling of supply voltage is one of the well-known methods for reducing leakage power. Data Retention Voltage (DRV) is the lower limit for the scaled voltage of SRAM. In this paper, we propose a modified analytical model for estimating the DRV of a 6T SRAM cell. The model is based on the sub-threshold current equations of the SRAM cell. The DRV of the 6T SRAM cell is computed using this model which is verified with the simulations carried out using the Cadence Virtuoso Tool. GPDK 45 nm, UMC 130 and 65 nm technology files are used for the validation of the model. The simulations are carried out for the 6T cell with different cell ratios and pull-up ratios. For each case, the DRV estimated from the model is nearly equal to the expected DRV calculated from simulations. The results matched well with the simulated results around 93%–79% whereas Qin’s model which matches only 75%–74%. This model shows better results than Qin’s model in terms of complexity and computation time. Furthermore, the proposed model is also validated for the calculation of DRV during process variation and shows better results.

A Novel Low-Power and Soft Error Recovery 10T SRAM Cell.

In SRAM cells, as the size of transistors and the distance between transistors decrease rapidly, the critical charge of the sensitive node decreases, making SRAM cells more susceptible to soft errors. If radiation particles hit the sensitive nodes of a standard 6T SRAM cell, the data stored in the cell are flipped, resulting in a single event upset. Therefore, this paper proposes a low-power SRAM cell, called PP10T, for soft error recovery. To verify the performance of PP10T, the proposed cell is simulated by the 22 nm FDSOI process, and compared with the standard 6T cell and several 10T SRAM cells, such as Quatro-10T, PS10T, NS10T, and RHBD10T. The simulation results show that all of the sensitive nodes of PP10T can recover their data, even when S0 and S1 nodes flip at the same time. PP10T is also immune to read interference, because the change of the '0' storage node, directly accessed by the bit line during the read operation, does not affect other nodes. In addition, PP10T consumes very low-holding power due to the smaller leakage current of the circuit.

T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training

Recently, on-device training has become crucial for the success of edge intelligence. However, frequent data movement between computing units and memory during training has been a major problem for battery-powered edge devices. Processing-in-memory (PIM) is a novel computing paradigm that merges computing logic into memory, which can address the data movement problem with excellent power efficiency. However, previous PIM accelerators cannot support the entire training process on chip due to its computing complexity. This article presents a PIM accelerator for end-to-end on-device training (T-PIM), the first PIM realization that enables end-to-end on-device training as well as high-speed inference. Its full-custom PIM macro contains 8T-SRAM cells to perform the energy-efficient in-cell AND operation and the bit-serial-based computation logic enables fully variable bit-precision for input data. The macro supports various data mapping methods and computational paths for both fully connected and convolutional layers, in order to handle the complex training process. An efficient tiling scheme is also proposed to enable T-PIM to compute any size of deep neural network with the implemented hardware. In addition, configurable arithmetic units in a forward propagation path make T-PIM handle power-of-two bit-precision for weight data, enabling a significant performance boost during inference. Finally, T-PIM efficiently handles sparsity in both operands by skipping the computation of zeros in the input data and by gating-off computing units when the weight data are zero. Finally, we fabricate the T-PIM chip in 28-nm CMOS technology, occupying a die area of 5.04 mm2, including five T-PIM cores. It dissipates 5.25–51.23 mW at 50–280 MHz operating frequency with 0.75–1.05-V supply voltage. We successfully demonstrate that T-PIM can run the end-to-end training of VGG16 model on the CIFAR10 and CIFAR100 datasets, achieving 0.13–161.08- and 0.25–7.59-TOPS/W power efficiency during inference and training, respectively. The result shows that T-PIM is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.02\times $ </tex-math></inline-formula> more energy-efficient than the state-of-the-art PIM chip that only supports backward propagation, not a whole training. Furthermore, we conduct an architectural experiment using a cycle-level simulator based on actual measurement results, which suggests that the T-PIM architecture is scalable and its scaled-up version provides up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$203.26\times $ </tex-math></inline-formula> higher power efficiency than a comparable GPU.

Design and Performance Analysis of 32 × 32 Memory Array SRAM for Low-Power Applications

Computer memory comprises temporarily or permanently stored data and instructions, which are utilized in electronic digital computers. The opposite of serial access memory is Random Access Memory (RAM), where the memory is accessed immediately for both reading and writing operations. There has been a vast technological improvement, which has led to tremendous information on the amount of complexity that can be designed on a single chip. Small feature sizes, low power requirements, low costs, and great performance have emerged as the essential attributes of any electronic component. Designers have been forced into the sub-micron realm for all these reasons, which places the leakage characteristics front and centre. Many electrical parts, especially digital ones, are made to store data, emphasising the need for memory. The largest factor in the power consumption of SRAM is the leakage current. In this article, a 1 KB memory array was created using CMOS technology and a supply voltage of 0.6 volts employing a 1-bit 6T SRAM cell. We developed this SRAM with a 1-bit, 32- × 1-bit, and 32 × 32 configuration. The array structure was implemented using a 6T SRAM cell with a minimum leakage current of 18.65 pA and an average delay of 19 ns. The array structure was implemented using a 6T SRAM cell with a power consumption of 48.22 μW and 385 μW for read and write operations. The proposed 32 × 32 memory array SRAM performed better than the existing 8T SRAM and 7T SRAM in terms of power consumption for read and write operations. Using the Cadence Virtuoso tool (Version IC6.1.8-64b.500.14) and 22 nm technology, the functionality of a 1 KB SRAM array was verified.

A 389 TOPS/W, Always ON Region Proposal Integrated Circuit Using In-Memory Computing in 65 nm CMOS

Neuromorphic vision sensors (NVSs) are key enablers of energy savings in Internet of Things (IoT)-based traffic monitoring and surveillance systems that exploit the temporal redundancy in video streams. However, for these scenarios, an object typically occupies a fraction of the full image frame leading to a significant spatial redundancy in the active image. Hence, there is a need for energy-efficient, dedicated hardware to detect the region of interests (RoI) to exploit spatial redundancy in the valid frames and reduce computations in the succeeding recognition modules. This article proposes a 9T-SRAM in-memory computing (IMC)-based region proposal (RP) network for event-based binary image (EBBI) frames from a NVS. The proposed 9T-SRAM cell enables a 1-D projection of objects on the horizontal and vertical axes of an image. An iterative and selective search (ISS) of the rising and falling edges of 1-D projection yields the coordinates of a bounding box encapsulating an object. To demonstrate the energy-saving and effectiveness of the algorithm, we fabricated the proposed architecture, RP integrated circuit (RPIC) in a 65 nm CMOS process. Tested with the video recordings from a Dynamic and Active-pixel Vision Sensor (DAVIS), the RPIC achieves a peak throughput of 1259 ft/s at 1 Meps event rate. Moreover, the proposed RP architecture achieves a high energy efficiency of 389 TOPS/W due to in-memory operation.

High-performance and highly-stable soft error resistant 12T SRAM cell for space applications

In this paper, a high-performance and highly-stable soft error resistant 12T (HPHS12T) SRAM cell is proposed. Based on polarity reversal design and NMOS stacked structure, the proposed HPHS12T cell can recover from any single event upsets (SEU) induced at all its sensitive nodes and even single event multiple-node-upsets (SEMNU) induced at its internal storage node pair Q-QN, while also having the maximum read static noise margin (RSNM) and write noise margin (WNM), as well as excellent write-ability. Though the HPHS12T cell exhibits a larger static hold power, it has the best overall performance of all the other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed cell a better choice for space applications.

DESIGN OF A 6T SRAM CELL WITH MINIMAL POWER USING CADENCE VIRTUOSO

It has proven challenging for VLSI designers to lower leakage power at the nanoscale level. This is because high- end gadgets, battery-operated portable pads, and other communication tools are in high demand. Memories are made up of static RAM and dynamic RAM. SRAM has had a significant impact on the worldwide VLSI market sinceit is preferred over DRAM because to its rapid read and write access times. Using a 6T static random access memory cell, this study's novel approach to lowering leakage current at various technologies has been put forth. To reduce the 6T SRAM cell leaking power, three source biasing techniques are used. At 45 nanometer and 90 nm technology nodes, the three techniques are NMOS diode clamping, PMOS diode clamping, and NMOS-PMOS diode clamping. The implementation of a 6T SRAM cell using the Multiple Threshold CMOS (MTCMOS) technique at 45nm technology is also emphasised in this article. Using the cadence virtuoso tool, the simulation is completed and different power dissipations are examined for 45 nm and 90 nm technologies, respectively, at supply voltages of 0.45 V and 0.9 V. Comparing PMOS clamping to the other two suggested techniques, an average power reduction of 82.19% was observed.

Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor

SRAM is a key component in many VLSI circuits for efficient storage data. Various researches have been performed on implementation of SRAM using Conventional CMOS, FinFET and GNRFET technologies. But, these methodologies generating the more number of faults with high power and delay consumption, tosolve this problem proposed10T SRAM cell is implemented with the CNTFET respectively. Present research involving CNTFET SRAM deals with leakage analysis and dealt with the dual hilarity characteristics. Fault introduction and analysis of faults were limited with CMOS SRAM. The detection algorithms and circuits possess limitations in terms of detecting the current at nanoscales and restricted with CMOS SRAM. These limitations made us to pursue the research in these areas to bring novel ideas. The performance metrics evaluated and experimental analysis is made and it helps us to choose between various SRAMS. The simulation results shows that the proposed 10T SRAM consumes less delay and power compared to the 7T SRAM cell.

Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications

With technology scaling, transistor sizing as well as the distance between them, is decreasing rapidly, thereby reducing the critical charge of sensitive nodes. This reduction makes SRAM cells used for aerospace applications more susceptible to radiation as it can cause single-event upsets (SEUs) and also single-event multi-node upsets (SEMNUs). This article presents an energy-efficient dual-node-upset-recoverable 12T SRAM cell for low-power aerospace applications, EDP12T, in 65-nm CMOS technology. The proposed cell mitigates SEUs as well as SEMNUs. To judge the relative performance of EDP12T, a comparative study is made between it and other radiation-hardened cells: RHM12T, QUCCE12T, QUATRO12T, RHD12T, SRRD12T, RHPD12T, RSP14T, LWS14T, SAR14T, and S8P4N16T. EDP12T can recover from SEUs induced at all the sensitive nodes and from SEMNUs that have occurred at its internal node-pair. EDP12T exhibits better write performance than most of the comparison cells, it also consumes the least energy during write mode, and lower energy than most of the comparison cells during read mode. EDP12T exhibits a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.08\times /1.17\times /1.37\times /1.56\times /2.32\times $ </tex-math></inline-formula> higher read stability than S8P4N16T/RHPD12T/QUCCE12T/QUATRO12T/LWS14T. Additionally, EDP12T dissipates the lowest hold power among all the cells for comparison, except for RHM12T. These improvements are obtained by the proposed cell while consuming a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.03\times /1.06\times /1.07\times /1.08\times /1.14\times /1.43\times /2.01\times $ </tex-math></inline-formula> lower area than SAR14T/RHD12T/S8P4N16T/RSP14T/LWS14T/RHPD12T/SRRD12T. However, these advantages come with a slight penalty in the read delay.

A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture

A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture

A gate leakage current-powered loadless 4T SRAM with immunity against random dopant fluctuation and surface roughness in silicon-silicon dioxide interface

The sensitivities of the data hold, read and write performances for the gate leakage-powered loadless 4T SRAM cell on the variations in the MOSFETs’ gate leakage currents are examined by SPICE Monte Carlo simulations in 32 nm technology. The standard deviations in the gate leakage current variations are taken from the device simulation results in which the variations are caused by the random dopant fluctuation and the surface roughness in silicon-silicon dioxide interface. It is shown that the static noise margin (SNM) in the data hold state is 60 mV at 1 V power supply voltage for the −5σ cell with the MOSFETs’ threshold voltage variations taken into consideration. The read SNM and the write SNM are shown to be 160 mV and 440 mV for the −5σ cell, respectively, which are better than the 6TSRAM cell.

A Spintronic 2M/7T Computation-in-Memory Cell

Computing data-intensive applications on the von Neumann architecture lead to significant performance and energy overheads. The concept of computation in memory (CiM) addresses the bottleneck of von Neumann machines by reducing the data movement in the computing system. Emerging resistive non-volatile memory technologies, as well as volatile memories (SRAM and DRAM), can be used to realize architectures based on the CiM paradigm. In this paper, we propose a hybrid cell design to provide the opportunity for CiM by combining the magnetic tunnel junction (MTJ) and the conventional 6T-SRAM cell. The cell performs CiM operations based on stateful in-array computation, which has better scalability for multiple operands compared with stateless computation in the periphery. Various logic operations such as XOR, OR, and IMP can be performed with the proposed design. In addition, the proposed cell can also operate as a conventional memory cell to read and write volatile as well as non-volatile data. The obtained simulation results show that the proposed CiM-A design can increase the performance of regular memory architectures by reducing the delay by 8 times and the energy by 13 times for database query applications consisting of consecutive bitwise operations with minimum overhead.

Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques

This paper presents the sleepy keeper and drain gating technique to improve the performance of 10T SRAM cell. The behavior of 10T SRAM cell is evaluated using benchmarked industry standard GPDK 45nm Technology Node of the Cadence Virtuoso EDA tool. The performance is analyzed in terms of dynamic and static parameters of 10T SRAM cell and compared with 6T SRAM, where find the reduction in dynamic power and static power dissipation. Besides this, observed the reduction in leakage current using sleepy keeper and drain gating technique. The proposed modified topology applicable in single-ended write and differential read operation. The read delay product and the write delay product is decreased by 36.7 % and 67.5 %, respectively. The major goal of the suggested architecture is to provide the improved stability, reduction in delay, as well as reduction in leakage current.

Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell

Technology scaling is done in order to accommodate more and more transistors in today’s high performance VLSI circuits. These high-performance digital circuits demand large capacity of memory to accomplish faithful operations. However, at scaled technology, SRAM-cell stability is a major issue of concern. Also, increased integration density of these VLSI circuits causes increased power consumption. Leakage power in today’s VLSI circuits has become comparable to dynamic power consumption which also needs to be addressed. In this work, a Schmitt-trigger (ST) based 10T SRAM cell with single-ended-writing and differentially-read feature is proposed. The proposed cell offers enhanced stability and dissipates lower leakage power. Due to separate ports for writing and reading in the proposed cell, the conflict design requirement (which is a condition in conventional 6T cell) is eliminated. Schmitt-trigger based inverters in the proposed cell causes increased threshold voltage of the inverters resulting in enhanced cell stability during read operation. Simulation is carried out on TSPICE using a 65nm Predictive Technology Model (PTM). Results show that the proposed 10T cell provides a 1.7x larger Read static noise margin (RSNM) than the conventional 6T cell. Proposed 10T cell provides Write static noise margin (WSNM) of 155mV during write ‘0’ while 150mV during write ‘1’ operation, respectively, at 0.4V. At a supply voltage of 0.4V, the proposed 10T cell consumes 0.71x lesser static power as compared to that of a conventional 6T cell. However, proposed cell uses more transistors (10 transistors) as compared to that of the conventional 6T cell, therefore, our cell occupies large chip-area as compared to the conventional 6T cell.

Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic - and -Values

Complementary FET (CFET) is a promising booster for further area reductions in static random-access memory (SRAM) cells. However, the performance degrading by a series of parasitic parameters in these SRAM cells will diminish the scaling benefit introduced by new transistor architectures. In this article, we propose a universal methodology to determine the layout optimization direction of 6T static random-access memory (6T-SRAM) cells by studying the sensitivity of 6T-SRAM cell performance to various parasitic parameters. And adopt this method to optimize the CFET SRAM cell layout structure under the advanced nodes beyond 3 nm. The performances of CFET 6T-SRAM cells with different layout schemes are comparatively evaluated. It is found that the influence of the parasitic resistance on 6T-SRAM performances is double-sided, and parasitic resistances from transistor to power rail ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {pds}}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {pud}}$ </tex-math></inline-formula> ) and from access (AX) devices to bit-lines (BLs) ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm{bax}}$ </tex-math></inline-formula> ) have the most important effect on improving read noise margin (RNM) together with write margin (WM). The BL-first scheme with reduced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm{bax}}$ </tex-math></inline-formula> and increased <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm {pud}}$ </tex-math></inline-formula> is proven to have 76.3% improvement in WM and 122.5% decrease in write time (WT) compared to the BL-last scheme, and a 63.8% improvement in RNM compared to conventional nanosheet architecture. Further optimized <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\mathrm{bax}}$ </tex-math></inline-formula> in the buried-BL scheme is proven to have higher WM, as well as lower WT. The BL-first scheme and buried-BL scheme is proven to be the most efficient approach to boost CFET SRAM performance.

Single-Ended 8T SRAM cell with high SNM and low power/energy consumption

ABSTRACT This paper introduces an 8T single-ended SRAM cell to improve stability and decrease energy consumption. It cuts the pull-down path to the storage node written ‘1’, enhancing the write ability. It uses an isolated read path to enhance the read stability with low power and energy consumption. At a supply voltage of 0.5 V, the read static noise margin, write margin, read energy, and write energy of the proposed cell are superior by 320%, 233%, 12%, and 26%, respectively, compared to the conventional 6T. We performed 5,000 Monte Carlo simulations in the 32 nm technology to evaluate read yields. The results show that our cell has 6.9x more yields than the conventional 6T SRAM cell. Therefore, the proposed cell can be a good option for high stability and low power/energy applications.

Design and investigation of stability‐ and power‐improved 11T SRAM cell for low‐power devices

AbstractThe modern system‐on‐chips require stable and low‐power SRAM cells due to technology scaling and limited sources of energy. Therefore, a stability‐ and power‐improved 11T SRAM cell is proposed in this study. The proposed cell core is composed of a strong cross‐coupled structure of a conventional inverter with a N‐type stacked transistor and a Schmitt‐trigger (ST) with a double channel‐length pull‐up network. This coupled with a separate read path enhances the read static noise margin (RSNM). Moreover, a feedback‐cutting N‐type transistor is placed inside the cell core to improve the write static noise margin (WSNM)/write margin (WM). Though the presence of stacked transistors in access paths increases read delay (TRA)/write delay (TWA), it reduces leakage. This metric further minimizes with the aid of a stacked structure of latch core and double channel‐length of pull‐up transistor in the ST inverter. The moderate read/write frequency and single‐ended structure of the suggested cell result in low dynamic power. Simulated results by using 16‐nm CMOS at VDD = 0.7 V show that the proposed cell has the second‐best RSNM/WSNM, which is 4.65/1.44 times higher than that of the fully differential 8T (FD8T) cell, as the basic cell. Moreover, it reduces leakage power by at least 2.01 times and consumes moderate read/write power, nearly 1.44/1.81 times lower than that of FD8T cell, at the cost of 1.61 times area overhead. The proposed cell can eliminate read/write‐half‐select‐disturbance issues to support bit‐interleaving architecture to increase soft error immunity.