6T SRAM Cell Research Articles

A Reliable and high performance Radiation Hardened Schmitt Trigger 12T SRAM cell for space applications

In the vacuum of space, alpha particles and cosmic radiation can cause the node data to be altered, leading to data loss. When a radiation particle hits a vulnerable point of the typical 6T static random access memory (SRAM) cell, it results in the alteration of the stored data within the cell, leading to a single-event upset (SEU). Traditional 6T SRAM cannot withstand the extreme conditions present in space. Hence, it is imperative to develop an SRAM that can endure these challenging space conditions. To address the impact of SEUs, a Radiation Hardened Schmitt Trigger 12 transistor (RHST12T) SRAM cell is proposed in this paper. To gauge the comparative effectiveness of the proposed cell, it is compared with other radiation hardened SRAM cells, namely, QUCCE12T, WE-QUATRO, RHPD12T, and SRRD12T. Even if a radiation strike flips the node values, all of RHST12T sensitive nodes can recover their data. It shows up to 1.6×/45.32×/0.29 ×106× less read delay, write delay, and leakage power consumption, respectively as compared to other considered SRAM cells. It achieves up to 5.75×/3.09× better read and hold stability, respectively than the considered SRAM cells.

Low power 7T SRAM cell optimization with 45nm Technology

A new low power SRAM cell introduced that promises improved performance by adding extra circuitry to a 6T-SRAM cell. This new design features a 7T(seven-transistors) cell at 45nm size CMOStechnology, aiming to enhance power efficiency,stability, overall performance compared to older designs for low power memory operations. By optimize the size and implementing a novel write circuitry scheme, new (seven transistor)7T SRAM cell fullfill a significant 45% reduction in power consumption during memory operations when compared to the traditional 6T SRAM-based design. Furthermore, through CADENCE simulations, it is shown that this 7T SRAM cell is highly resistant to process variations, highlighting its robustness and reliability in real-world applications.

Study on Single Event Upset and Mitigation Technique in JLTFET‐Based 6T SRAM Cell

Study on Single Event Upset and Mitigation Technique in JLTFET‐Based 6T SRAM Cell

The Performance of SRAM Cell Topologies with 6 T, 7 T, 8 TAnd 9 T Technologies at 45 Nm Technology node

Numerous SRAM cell architectures employing 45nm technology were simulated in the Tanner tool used for this inquiry. In every arrangement, variables like read latency, write delay, power read, power write consumption, read static noise margin (RSNM), and write static noise margin (WSNM) were examined. Of all the designs, the 7T SRAM cell stands out for having the lowest power read utilization. Nevertheless, compared to the 6T SRAM cell, the 8T SRAM cell displayed a 44.15% reduction in power write power.The 9T SRAM cell exhibited the lowest write latency of all the cells tested.Among all the simulated devices, the traditional 6T SRAM cell also showed the highestRSNM value. There was discovered the 8T SRAM cell's WSNM.

A FinFET-based low-power, stable 8T SRAM cell with high yield

Modern battery-enabled systems, such as IoT, require SRAM cells that can maintain data and respond quickly to requests. However, achieving low-power and stable SRAM cells, which are essential for IoT systems, is not possible with CMOS technology due to scaling issues. As a result, new nanoscale devices, such as FinFET, have been introduced as a potential replacement for CMOS in SRAM design. This paper presents a new FinFET-based 8 T SRAM cell with separate reading and writing paths. The cell uses read-decoupling and write-assist pull-down path cut techniques to improve read stability and writability, respectively. Single-ended reading and writing structures reduce power consumption, and stacking transistors, along with read bitline leakage elimination, reduces leakage power dissipation. The proposed cell’s efficiency is evaluated using HSPICE simulator with 10-nm FinFET technology and is compared with conventional 6 T, single-bitline 7 T (SB7T), single-ended 8 T (SE8T), and transmission gate read-decoupled 9 T (TRD9T) SRAM cells at VDD = 0.35 V. The proposed cell improves read stability by 2.59×/1.04 × and enhances writability by 1.38×/1.01 × compared to 6 T/TRD9T and 6 T/SB7T, respectively. It also reduces read power by 28.25 %/19.60 % compared to the 6 T/SB7T and reduces write power by at most 33.40 % and at least 5.46 %. Moreover, the leakage power is reduced by at least 5.80 %. However, the proposed cell increases read/write delay by 1.77×/1.40 × and shows 1.23 × larger layout area compared to 6 T.

A soft error upset hardened 12T-SRAM cell for space and terrestrial applications

Various charged particles in space, including alpha particles, neutrons, heavy ions, and photons, pose reliability and stability concerns for memory circuits. These particles also create an ion track in the memory chip, disrupting the storage bit. The standard 6T SRAM is particularly susceptible to these disturbances. Several researchers suggest employing radiation-hardened SRAM cells to solve this problem. Most studies examine the inclusion of redundant nodes in the memory cell to recover the lost bit. This paper shows a new SEUH-12T SRAM memory cell with redundant nodes to deal with the soft error problem. The proposed SEUH-12T memory cell performance is compared to that of reliable radiation-hardened memory cells such as Quatro-10T, We-Quatro-12T, QCCS-12T, STS-10T, RHMC-12T, and RHWC-12T. The proposed SEUH-12T cell protects against single and multiple node disruptions by considering minimum sensitive nodes layout area separation concept. Furthermore, proposed SEUH-12T exhibits 8.5×/ 6.3×/ 5.6×/ 1.4×/ 1.2×/ 1.4×/ 1.04× times greater read stability than existing 6T-SRAM/ Quatro-10T/ We-Quatro-12T/ QCCS-12T/ STS-10T/ RHMC-12T/ RHWC-12T memory cells.

Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications

Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications

Schmitter trigger-based single-ended stable 7T SRAM cell

Schmitter trigger-based single-ended stable 7T SRAM cell

Soft Error Simulation of Near-Threshold SRAM Design for Nanosatellite Applications

This paper presents the benefit of the near-threshold design of random-access memory (SRAM) design to reduce software errors during very low-power operations in nanosatellites. The near-threshold design is based on an optimization of the use of the Schmitt trigger structure for a 45 nm technology. The results of the soft error susceptibility of the optimized design are compared to a standard 6T SRAM cell. These two designs are modeled and validated by comparing the results with experimental measurements of both static noise margin (SNM) and single event upset (SEU). The optimized circuit reduces the multiple upsets occurrence from 95% down to 14%. Based on the use of simulation tools, the paper demonstrates that the near-threshold design of SRAM is an excellent candidate for the radiation point of view for agile nanosatellites. The results computed for the near-threshold SRAM device demonstrate an improvement of a factor of up to 25 of the soft error rate (SER) in a GEO orbit.

Performance analysis of OTFT-based SRAM topologies

In terms of mechanical flexibility, organic SRAM offers better designs and a commercially feasible option with the ability to deliver acceptable performance. This paper investigates the implementation of different SRAM topologies based on organic thin film transistors (OTFTs). In this work, a compact spice model is used to simulate pOTFT and nOTFT in LTSpice software. Time delays, power consumption, the power delay product (PDP), and static noise margin (SNM) for read and write operations are calculated, and a comparative analysis of OTFT based 6T, 7T, 8T, and 9T SRAM topologies is performed. Among different topologies, 9T OTFT SRAM cell achieves a 1.67× increase in SNM, compared to conventional 6T OTFT-based SRAM cell. The highest figure of merit value of 9T SRAM cell indicates its suitability for various applications.

An 8T PA Attack Resilient NVSRAM for In-Memory-Computing Applications

The proposed 8T Non-Volatile SRAM (NVSRAM) is designed to be resistant to power analysis (PA) attacks and is suitable for in-memory computing (IMC) applications. Our design uses a two-phase write operation instead of the traditional single-phase write operation, which reduces the correlation between stored data and power consumption during writing and provides resilience against PA attacks. It provides a mean energy difference (MED) of 5aJ, which is 1000 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> less compared to available 6T SRAM cells. The proposed cell also utilizes a common Spin transfer torque (STT) current for both magnetic tunnel junctions (MTJs), which results in more energy efficient and faster store operations. The store operation becomes 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> more energy efficient and 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> faster compared to the available state of the art NVSRAM Cells. The Symmetrical structure of proposed cell and two stage store/restore operation provide PA attack resiliency during store and restore mode of NVSRAM. Additionally, the proposed cell performs IMC for XNOR computation by collocating the weights and activations stored in the same bit cell.

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis.

Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., <12b, show lower accuracy but higher power efficiency. An input precision of 8b achieves implementation requirements. The maximum performance reported is 7.49 TOPS at 330 MHz, while custom SRAM-based performance has shown a maximum of 5.6 GOPS at 100 MHz. The second part of this article analyzes the FinFET 6T-SRAM as one of the critical components in determining overall performance of an AI computing system. We have investigated the FinFET 6T-SRAM cell performance and limitations as dictated by the FinFET technology-specific parameters, such as sizing, threshold voltage (Vth), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values.

Radiation hardened 12T SRAM cell with improved writing capability for space applications

This paper presents an inventive and extremely dependable radiation-hardened by-design (RHBD) 12T SRAM Cell with enhanced writing capability (RHWC-12T) for a space radiation environment. The Proposed RHWC-12T SRAM is designed on Cadence Virtuoso with quad-storage nodes and simulated in 45-nm CMOS technology with the supply voltage of 1.1 V and 27∘C operating temperature. The proposed cell is tolerant to both 0 to 1 and 1 to 0 SEUs (Single event upsets). Also, it provides better speed and stability compared to the other considered SRAM cells such as 6T, 10T Dohar, Quatro, We-Quatro, QUCCE-12T, and NQuatro. According to simulation findings, the proposed SRAM cell provides 1.053× better writing stability than the 10T Dohar SRAM cell. In addition, the write access time improves by 3.56× with 1.36× area overhead than 10T Dohar SRAM cell.

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x &amp; 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell.

Leakage power attack resilient Schmitt trigger based 12T symmetric SRAM cell

In this paper, a new 12T Schmitt trigger based SRAM cell is proposed in 40 nm technology. The proposed SRAM cell is resilient to leakage power attack (LPA), which is one of the main concern in side-channel attack (SCA). The proposed SRAM cell is designed by incorporating two more transistors to the Schmitt Trigger based 10T SRAM cell and is having equal leakage current when the storage node (Q) is storing 0 and 1, thereby achieving the overall distribution overlap percentage of 97.5% as compared to 0.09% of overlap in case of Schmitt Trigger based 10T SRAM. The Hold Static Noise Margin (HSNM), Read Static Noise Margin (RSNM) and Write Margin (WM) of the proposed design are also increased by 38.14%, 58.11% and 20.29% respectively as compared to 6T. Moreover, the WTP of the LPAR 12T is 1.07× greater as compared to the conventional 6T SRAM cell.

Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell

This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.

DESIGN AND IMPLEMENTATION OF SRAM 6T FOR 2 BYTES

SRAM has become a significant segment in numerous VLSI Chips because of their huge stockpiling thickness and little access time. SRAM has gotten the theme of impressive research because of the fast improvement for low power, low voltage memory structure during late years because of increment interest for scratch pad, workstations, IC memory cards and specialized gadgets. SRAMs are broadly utilized for versatile and PC applications as both on chip and off-chip recollections, in view of their accessibility and low backup spillage. The fundamental target of this paper is assessing execution regarding Power utilization, deferral and Signal to Noise Margin of existing 6T SRAM cell in 45nm and 180nm innovation.

Design of a high performance CNFET 10T SRAM cell at 5nm technology node

This article proposes a CNFET 10T SRAM cell based on Stanford Virtual Source model at 5nm technology node, through optimization design and simulation analysis to select optimum gate widths of transistors to ensure best performance in terms of stability, speed and power consumption. We compare the proposed 10T CNFET SRAM with the optimized 6T CNFET SRAM in [9]. It was found that the timing and power characteristics of the proposed 10T SRAM cell is better than that of the 6T structure, the static power consumption is greatly reduced while the RSNM is improved by 93.5%, read and write EDP are improved by 68.5% and 96%, respectively.

CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell

A new carbon nano-tube field-effect transistors (CNTFETs) based Power Efficient and Robust 8T (PER-8T) SRAM cell is proposed to reduce sub-threshold leakage currents, data dependency by improving RBL swing due to which RSNM is improved. Leakage power is reduced by using only single pull-up transistor with High V t in storage latch. Half-select issue is eliminated since proposed work uses de-coupled read port. This CNTFET based proposed PER-8T cell is analysed for performance parameters like power, delay and stability and compared to 8T SRAM cells at 45 nm technology. All simulations are performed at supply voltage of 0.9 V considering Stanford Virtual Source CNTFET(VS-CNTFET) model. It shows that RSNM and WSNM are improved by 12.07%, 14.85%, 56% and 46.46%, 20.39%, 66.05% compared to single ended 8T SRAM cells available in recent literature. Effects of VS-CNTFET parameters such as dielectric material, temperature, oxide thickness and carbon nano tube diameter values on hold power is analysed and best values are considered. The cadence tool is used for measuring all design metrics at room temperature of 25 °C.

A Single-Ended 9T SRAM Cell With Improved Noise Margin for Low-Power Applications Used in LEDoS

As a silicon-based microdisplay for Augment reality (AR), the high power dissipation of digital CMOS driver is a significant barrier to approaching the higher performance of microdisplay. In this paper, a new low-power SRAM cell with a single bitline is proposed to reduce the power dissipation of digital CMOS drivers. Compared with conventional differential 6T SRAM cell, the proposed 9T uses the single-ended read/write and read/write separation technology by reducing bitline and adding word lines, and write/read static noise margin (WSNM/RSNM) has been improved while the power dissipation is reduced effectively by stacking effect. When VDD is 0.8 V, the proposed cell achieves 1.4× and 2.2× improvement in WSNM and RSNM compared to D6T. Besides, the proposed cell consumes 1.4× less power during hold mode compared to D6T at VDD=0.8 V.