65-nm Complementary Metal-oxide Semiconductor Technology Research Articles

Highly Miniaturized, Low-Power CMOS ASIC Chip for Long-Term Continuous Glucose Monitoring.

The objective of this work is to develop a highly miniaturized, low-power, biosensing platform for continuous glucose monitoring (CGM). This platform is based on an application-specific integrated circuit (ASIC) chip that interfaces with an amperometric glucose-sensing element. To reduce both size and power requirements, this custom ASIC chip was implemented using 65-nm complementary metal oxide semiconductor (CMOS) technology node. Interfacing this chip to a frequency-counting microprocessor with storage capabilities, a miniaturized transcutaneous CGM system can be constructed for small laboratory animals, with long battery life. A 0.45 mm × 1.12 mm custom ASIC chip was first designed and implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology node. This ASIC chip was then interfaced with a multi-layer amperometric glucose-sensing element and a frequency-counting microprocessor with storage capabilities. Variation in glucose levels generates a linear increase in frequency response of this ASIC chip. In vivo experiments were conducted in healthy Sprague Dawley rats. This highly miniaturized, 65-nm custom ASIC chip has an overall power consumption of circa 36 µW. In vitro testing shows that this ASIC chip produces a linear (R2 = 99.5) frequency response to varying glucose levels (from 2 to 25 mM), with a sensitivity of 1278 Hz/mM. In vivo testing in unrestrained healthy rats demonstrated long-term CGM (six days/per charge) with rapid glucose response to glycemic variations induced by isoflurane anesthesia and tail vein injection. The miniature footprint of the biosensor platform, together with its low-power consumption, renders this CMOS ASIC chip a versatile platform for a variety of highly miniaturized devices, intended to improve the quality of life of patients with type 1 and type 2 diabetes.

A Method for Leakage Current and Power Reduction of Buffer in 65-nm CMOS Technology Based on the Pileup-Effect

In small-size Complementary Metal Oxide Semiconductor (CMOS) technology, the size of Very Large-Scale Integration (VLSI) below 90nm becomes higher and higher due to the enhancement of the short channel effect of transistors. CMOS Buffer is a very common circuit unit in VLSI. In this paper, a Pileup effect transistor (PET) is proposed to reduce the subthreshold leakage current of the CMOS buffer. The main principle of PET technology is to reduce the voltage difference between gate and source and the voltage difference between drain and source by lowering the voltage of source so as to reduce the subthreshold leakage current. Through simulation-based on Cadence and Taiwan Semiconductor Manufacturing Company (TSMC) N65 library, PET technology can reduce leakage current power consumption by about one-twelfth of the original while maintaining the function of the original CMOS buffer. PET technology has also been found to reduce current consumption in the transition state by about 40%.

Characterization of the Total Charge and Time Duration for Single-Event Transient Voltage Pulses in a 65-nm CMOS Technology

This article presents the circuits and heavy-ion irradiation test results of a single-event transient (SET) measurement chip in a 65-nm complementary metal–oxide–semiconductor (CMOS) technology. The measurements contain two parts: total SET ionization charge and SET pulse duration. Transistors with different types and dimensions were implemented as victim devices to evaluate how transistor parameters impact the SET effects. Additionally, SET variation from different supply voltages was also investigated. The test chip has been tested under a heavy-ion beam with an effective linear energy transfer (LET) from 20.4 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$88.35~\text {MeV}\cdot \text {cm}^{2}$ </tex-math></inline-formula> /mg using a 0°–45° incidence angle.

Dual-Band CMOS RF Front-End Employing an Electrical-Balance Duplexer and N-Path LNA for IBFD and FDD Radios

This article proposes a dual-band complementary metal-oxide-semiconductor (CMOS) radio frequency (RF) front end employing a hybrid transformer-based electrical-balance duplexer (EBD) and N-path filter embedded low-noise amplifier (LNA) for both in-band full duplexing (IBFD) and frequency-division duplexing (FDD) radios. To securely obtain sufficient self-interference cancellation (SIC) or transmitter (TX) leakage rejection in IBFD and FDD modes of the EBD at both low-band (LB) (0.7-1 GHz) and mid-band (MB) (1.8-2.2 GHz) frequency ranges, a band-switchable hybrid transformer is designed with a finely adjustable balance network to control the antenna impedance variations. In addition, the four-phase N-path LNA is utilized to further offer TX leakage rejection in the FDD operation. This RF front-end is fabricated using a 65-nm CMOS technology and is mainly characterized by long-term evolution frequency bands. The demonstrated design achieves SIC and TX leakage rejection greater than 55 dB for IBFD and FDD modes of all measured frequency bands, which has a maximum power handling capability of +25 dBm. Furthermore, the design attains voltage gains greater than 8.7 dB for LB and 3.7 dB for MB, noise figures of 10.4 dB for LB and 12.1 dB for MB, out-of-band (OB) P1dBs greater than +21.4 dBm for LB and +21.5 dBm for MB, and OB IIP3s greater than +39.7 dBm for LB and +43.1 dBm for MB. It draws a bias current of 23.8 mA from the LNA and output buffer with a nominal supply of 1.2 V and has an active area of approximately 2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Wide Field-of-View Locating and Multimodal Vital Sign Monitoring Based on ${X}$ -Band CMOS-Integrated Phased-Array Radar Sensor

In this article, an X -band complementary metal-oxide-semiconductor (CMOS)-integrated phased-array radar sensor is proposed to enable the subject localization and multimodal vital sign monitoring. With the accurate beam-steering (ABS) technique realized by both true-time delay and phase shifting at the transmitter, the phased-array radar sensor achieves 60° steering coverage for the locating and monitoring on the targeted subjects with fine beam-steering precision. With the interferometric time-phase analysis (ITPA) algorithm adopted to the dechirped signal at the receiver, the vital signs and falling are detected by the radar sensor. Fabricated in 65-nm CMOS technology, the radar sensor occupies 5.8 mm 2 of silicon area and consumes 740.7-mW power. A series of experiments was carried out to demonstrate the capabilities of the prototype radar sensor on localizing the targeted subjects, discerning vital signs, and detecting falling in a wide field of view (FoV).

Optimum design of a new ultra-wideband LNA using heuristic multiobjective optimization

This paper presents an optimum design of an ultra-wideband (UWB) 2.5–10.5-GHz low-noise amplifier (LNA) in 180-nm and 65-nm radiofrequency (RF)-complementary metal–oxide–semiconductor (CMOS) technology. A novel input matching network employing resistive–inductive feedback and a noise-canceling technique is proposed to achieve broadband matching as well as a low noise figure (NF). Moreover, a current-reused structure and the inductive peaking technique are applied in the proposed LNA to reduce its power consumption and provide high, flat gain. The proposed UWB-LNA is optimized using heuristic multiobjective optimization based on inclined planes system optimization (IPO) and particle swarm optimization (PSO) as simulation-based evolutionary techniques. The proposed UWB-LNA is designed and simulated using HSPICE and Cadence Spectre RF. The postlayout simulation results show an input return loss (S11) of less than −10 dB, a flat power gain (S21) of 13.2 ± 0.5 and 14 ± 0.5 dB, and an NF below 5 and 2.5 dB over the whole UWB band when implemented in 180-nm and 65-nm CMOS technology, respectively. The UWB-LNA consumes 7.2 and 9.5 mW from a 1.8-V power supply when implemented in 180-nm and 65-nm CMOS technology, respectively.

A Chopper Stabilization Audio Instrumentation Amplifier for IoT Applications

A low-noise instrumentation amplifier dedicated to a nano- and micro-electro-mechanical system (M&amp;NEMS) microphone for the use in Internet of Things (IoT) applications is presented. The piezoresistive sensor and the electronic interface are respectively, silicon nanowires and an instrumentation amplifier. To design an instrumentation amplifier for IoT applications, different trade-offs are discussed like power consumption, gain, noise and sensitivity. Because the most critical noisy block is the amplifier, a delay-time chopper stabilization (CHS) technique is implemented around it to eliminate its offset and 1/f noise. The low-noise instrumentation amplifier is implemented in a 65-nm CMOS (Complementary metal–oxide–semiconductor) technology. The supply voltage is 2.5 V while the power consumption is 0.4 mW and the core area is 1 mm2. The circuit of the M&amp;NEMS microphone and the amplifier was fabricated and measured. From measurement results over a signal bandwidth of 20 kHz, it achieves a signal-to-noise ratio (SNR) of 77 dB.

A Charge-Sharing-Based Two-Phase Charging Scheme for Zero-Crossing-Based Integrator Circuits

As an effort to improve the energy efficiency of switched-capacitor circuits, zero-crossing- based integrators (ZCBI) that consist of zero-crossing detectors and charging circuits have been proposed. To break the trade-off between accuracy and speed, ZCBI typically employs a two-phase charging scheme that relies on an additional threshold for zero-crossing detection. This paper proposes a simpler realization method of the two-phase charging scheme by means of charge sharing. To demonstrate feasibility of the proposed method, we designed and fabricated a second-order delta-sigma modulator in 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The measurement results show that the modulator exhibits a peak signal-to-noise-and-distortion ratio (SNDR) of 46.3 dB over the bandwidth of 156 kHz with the power consumption of 684 µW. We also designed the same modulator in 65-nm CMOS technology and simulation results imply that the proposed circuit is able to achieve a much better energy efficiency in advanced technology.

A 3.1–10.6-GHz 57-Bands CMOS Frequency Synthesizer for UWB-Based Cognitive Radios

An ultra-wideband (UWB)-based cognitive radio (CR) is a promising technique to utilize 3.1–10.6-GHz band efficiently for high data-rate short-range wireless connectivity even in overcrowdedness of the frequency spectrum. Frequency synthesizers tailored to the UWB-based CR should provide wide lock range, multiple frequency bands, and low in-band spurs while consuming low power. This paper investigates a low power, wide lock range, integer-N frequency synthesizer approach with 132-MHz frequency step and 57 subbands in the UWB band. Two-stage supply regulated differential ring oscillator provides linear and wide tuning range with voltage controlled oscillator gain of 22.5 GHz/V and low supply-noise sensitivity. A modular true-single-phase-clock programmable divider achieves wide operating frequency range of 0.1–6.5 GHz and power efficiency of 6.25 GHz/mW by compensating leakage current at the dynamic nodes with conditional latches. Replica-based digital calibration reduces the current mismatch of the charge pump to <1% for low in-band reference spurs of <−60 dBc. A frequency synthesizer test chip was fabricated in 65-nm complementary metal–oxide–semiconductor technology. The active area of the frequency synthesizer is 0.12 mm2. It achieves <−30-dBc integrated phase noise and enables the UWB-based CR to get bit error rate of <10−3 while consuming <−10.1 mW.

A super class-AB adaptive biasing amplifier in 65-nm CMOS technology

ABSTRACTThis paper presents a class-AB amplifier with enhanced transconductance and slew rate using adaptive biasing technique and new drivers. The adaptive biasing configuration provides a tail current linked to the input signal in order to increase the slew rate during slewing phase. In addition, the new structure benefits from new drivers to enhance the transconductance which are supported by adaptive biasing configuration. These enhancement techniques lead to the input and output class-AB operations for fast settling applications. The proposed structure is simulated in 65-nm complementary metal-oxide semiconductortechnology which shows a 16.2-dB enhancement in the DC gain and a 72% reduction in the settling time compared to the conventional structure.

A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes

Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

A novel diode string triggered gated-PiN junction device for electrostatic discharge protection in 65-nm CMOS technology**Project supported by the National Basic Research Program of China (Grant No. 2011CBA00606).

A novel diode string-triggered gated-PiN junction device, which is fabricated in a standard 65-nm complementary metal-oxide semiconductor (CMOS) technology, is proposed in this paper. An embedded gated-PiN junction structure is employed to reduce the diode string leakage current to 13 nA/μm in a temperature range from 25 °C to 85 °C. To provide the effective electrostatic discharge (ESD) protection in multi-voltage power supply, the triggering voltage of the novel device can be adjusted through redistributing parasitic resistance instead of changing the stacked diode number.

Impact of Total Ionizing Dose on the Data Retention of a 65 nm SONOS-Based NOR Flash

In this paper, the impact of total ionizing dose on the data retention behavior of a silicon-oxide-nitride-oxide-silicon-based NOR flash nonvolatile memory is studied for the first time on a deep sub-micron 65-nm complementary metal-oxide semiconductor technology node. The fundamental nonvolatile single-level cell memory element utilizes uniform Fowler-Nordheim (F-N) tunneling for both program and erase operations. The data retention behavior is investigated on a 4-Mb NOR Flash-based memory array at space-level total ionizing dose (TID) exposures up to 500 krad. Excessive TID exposure reduces the program-erase window but improves the thermal emission coefficient and, hence, improves data retention.

Polarisation analysing complementary metal‐oxide semiconductor image sensor in 65‐nm standard CMOS technology

In the present study, the authors demonstrate a complementary metal-oxide semiconductor (CMOS) image sensor implemented with on-chip polarisers using 65-nm standard CMOS technology. The polariser is composed of metal wire grids made of metal wires fabricated by the CMOS process. An extinction ratio of 18.8 dB was obtained for a single pixel with an on-chip polariser, where the line/space widths have the finest pitch obtainable by 65-nm technology. Electrical crosstalk between pixels is reduced by over 25% using a guard ring structure. Polarisation imaging by the sensor was also performed.

Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology

In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.