65nm CMOS Research Articles

Power-Aware Quantization in Analog In-Memory Computing With STT-MRAM Macro

Analog in-memory computing (AiMC) reduces the cost of data transfer by processing data inside memory. Compared with other emerging nonvolatile memories, AiMC with magnetic random-access memory (MRAM) shows potential with logic compatible supply voltage, small variability issues, and high endurance. However, the analog output of the array must be converted to digital using an analog-to-digital converter (ADC), which significantly offsets the benefits of AiMC. This paper presents power-aware quantization circuits in AiMC with spin transfer torque MRAM (STT-MRAM) macro, in which a successive approximation register (SAR) ADC with reconfigurable 3/4-bit resolution and 250MS/s sampling rate addresses the need of high speed and low power for AiMC. By using 28-nm CMOS process, simulation results show that the proposed ADC consumes only 31.6 μW at a 900mV supply and 250MS/s. 10.4-25.7 TOPS/W is realized with 2-bit input, 1-bit weight, and 4-bit output convolution neural network (CNN).

Design of a Ka-band power amplifier

This paper introduces the design of a type of power amplifier working in the Ka-band, which has three stages based on 45nm CMOS technology. The operating frequency is 25-27GHz, and it has good efficiency and linearity. Among them, the driving stage adopts a cascode structure, the power stage adopts common source structure, and the matching network adopts a transformer structure. Using Cadence Virtuoso for simulation at the operating voltage of 1.8V, power gain of the single-ended power amplifier is 44.76 dB, saturation output power is 14.66 dBm, the output power at the 1dB compression point is 12.9dBm, and corresponding power-added efficiency is 22.19%.

A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology

A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology

A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter

A low-power low-jitter phase-locked loop (PLL) with phase noise improvement for radio frequency transceivers is presented in this paper. The in-band phase noise and out-of-band phase noise are both reduced due to the time-amplifying technique and the class-C voltage-controlled oscillator (VCO), respectively. In addition, a low current mismatch charge pump (CP) is used here to guarantee a low reference spur. The proposed PLL is fabricated in a 65-nm CMOS mixed-signal process with an area of 0.220 mm2, and the reference clock is 150 MHz. The measurement results show that this PLL operates at 1-V supply voltages and achieves 8.5–10.3-GHz tuning range, 407.807-fs integrated jitter at 9.6 GHz, 7.20-mW total power consumption, resulting in a −239.22-dB figure-of-merit (FoM). The measured reference spur is −51.27 dBc at a 150-MHz offset frequency.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

This paper presents an energy efficient two-step hybrid-domain successive approximation register (SAR) analog-to-digital converter (ADC). Comparator offset calibration and kickback noise reduction techniques are proposed to maintain the high dynamic range and elevated residual signal quality of the coarse ADC. A feedback adjustment technology is proposed to reduce energy consumption of voltage-to-time converter (VTC). The VTC offset and LSB gain error between the coarse ADC and fine time-to-digital converter (TDC) are calibrated to ensure the gain accuracy. The proposed SAR ADC is designed in a 40-nm CMOS process and occupies 0.0363 mm2 silicon area. The post-simulation results show the proposed ADC achieved a spurious-free dynamic range (SFDR) of 74.8 dB and a signal-to-noise and distortion ratio (SNDR) of 56.42 dB at 0.4 V supply voltage and Nyquist input rate. The operating frequency scales from 100 kS/s to 5 MS/s. The converter has a power supply range of 0.4–0.8 V, and the figure of merit (FOM) is 4.85–10.6 fJ/conversion step.

A SAR ADC for multichannel synchronous signal acquisition

A synchronous sampling multichannel ADC is proposed to sample several signals at the same time and digitize the sampled signals in sequence. Instead of using multiple ADCs or multiple samplers, a modified SAR ADC with multiple capacitive DACs is applied to largely save area and reduce gain and offset mismatches between channels. A common-mode voltage resampling technique is proposed to reduce crosstalk errors between the multiple input signals below the ADC noise floor. To verify the ADC structure, a 10-bit 4-channel SAR ADC has been prototyped and implemented with a 180-nm CMOS technology. The ADC area is 0.325 mm2 (without PAD). At the sampling frequency of 250 kHz per channel, it uses 62 μW to achieve 9.38 ENOB for four input signals. The resolutions of the four channels are mainly limited by the DAC performances.

High-speed and energy-efficient asynchronous carry look-ahead adder.

Addition is a fundamental computer arithmetic operation that is widely performed in microprocessors, digital signal processors, and application-specific processors. The design of a high-speed and energy-efficient adder is thus useful and important for practical applications. In this context, this paper presents the designs of novel asynchronous carry look-ahead adders (CLAs) viz. a standard CLA (SCLA) and a block CLA (BCLA). The proposed CLAs are monotonic, dual-rail encoded, and are realized according to return-to-zero handshake (RZH) and return-to-one handshake (ROH) protocols using a 28-nm CMOS process technology. The proposed BCLA has a slight edge over the proposed SCLA, and the proposed BCLA reports the following optimizations in design metrics such as cycle time (delay), area, and power compared to a recently presented state-of-the-art asynchronous CLA for a 32-bit addition: (i) 32.6% reduction in cycle time, 29% reduction in area, 4.3% reduction in power, and 35.5% reduction in energy for RZH, and (ii) 31.4% reduction in cycle time, 28.9% reduction in area, 4.4% reduction in power, and 34.4% reduction in energy for ROH. Also, the proposed BCLA reports reductions in cycle time and power/energy compared to many other asynchronous adders.

A High Performance I/Q Zero-IF Mixer with IIP2 Calibration Technique in 45nm SOI CMOS

This paper presents a high performance I/Q zero intermediate frequency (IF) mixer with a second-order input intermodulation point (IIP2) calibration technique in 45nm SOI CMOS process. A behavioral model of the mixer is established to analyze the sources of the second-order intermodulation distortion (IMD2). Based on the analysis, a high accuracy load resistance modulation array is applied to achieve excellent IIP2 performance. The frequency of the local oscillator (LO) signal is 3.5GHz, while the RF input signal frequency range is 3.4GHz∼3.6GHz. Simulation results show that the proposed zero-IF mixer achieves a conversion gain of more than 9.2dB with the input 1dB compression point of -11.28dBm. Noise figure is about 16.9dB at 10kHz and lower than 11.6dB at the frequency above 1MHz. The IIP2 of the circuit is larger than 66dBm after the calibration, which increases more than 40dBm.

Dense, 11 V-Tolerant, Balanced Stimulator IC with Digital Time-Domain Calibration for 100 nA Error.

This article presents a multichannel neurostimulator implementing a novel charge balancing technique to achieve maximal integration. Safe neurostimulation demands accurate charge balancing of the stimulation waveforms to prevent charge build-up on the electrode-tissue interface. We propose digital time-domain calibration (DTDC), which adjusts the second phase of the biphasic stimulation pulses digitally, based on a one-time characterization of all stimulator channels with an on-chip ADC. Accurate control of the stimulation current amplitude is loosened in exchange for time-domain corrections, relieving circuit matching constraints and consequentially saving channel area. A theoretical analysis of DTDC is presented, establishing expressions for the required time resolution and the new, relaxed circuit matching constraints. To validate the DTDC principle, a 16-channel stimulator was implemented in 65 nm CMOS, requiring only 0.0141 mm 2 area/channel. Despite being implemented in a standard CMOS technology, 10.4 V compliance is achieved for compatibility with high-impedance microelectrode arrays typical for high-resolution neural prostheses. To the authors' knowledge, this is the first stimulator in a 65 nm low-voltage process achieving over 10 V output swing. Measurements after calibration show the DC error is successfully reduced below 96 nA on all channels. Static power consumption is 20.3 µW/channel.

An 80-GHz DCO utilizing improved SC ladder and promoted DCTL-based hybrid tuning banks

An 80-GHz DCO based on modified hybrid tuning banks is introduced in this paper. To achieve sub-MHz frequency resolution with reduced circuit complexity, the improved circuit topology replaces the conventional circuit topology with two binary-weighted SC cells, enabling eight SC-cell-based improved SC ladders to achieve the same fine-tuning steps as twelve SC-cell-based conventional SC ladders. To achieve lower phase noise and smaller chip size, the promoted binary-weighted digitally controlled transmission lines (DCTLs) are used to implement the coarse and medium tuning banks of the DCO. Compared to the conventional thermometer-coded DCTLs, control bits of the proposed DCTLs are reduced from 30 to 8, and the total length is reduced by 34.3% (from 122.76 to 80.66 μm). Fabricated in 40-nm CMOS, the DCO demonstrated in this work features a small fine-tuning step (483 kHz), a high oscillation frequency (79–85 GHz), and a smaller chip size (0.017 mm2). Compared to previous work, the modified DCO exhibits an excellent figure of merit with an area (FoMA) of –198 dBc/Hz.

A 14-bit 1-GS/s Pipelined-SAR ADC in 28-nm CMOS with Foreground and Background Calibration

A 14-bit 1-GS/s Pipelined-Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in 28-nm CMOS is presented in this paper. In the initial phase, a pair of SAR ADCs employing the Time-Interleaved (TI) technique are employed to attain the necessary sampling rate. A multi-comparators structure is used to increase the speed and improve the mismatch. We have implemented a foreground calibration technique to address capacitor mismatch, optimizing its processing logic to enhance the chip’s speed. The interstage operational amplifier adopts a two-stage structure. Some structural changes are presented to optimize its bandwidth and phase margin. A background calibration method for gain error is implemented. In the subsequent phase, we employ four SAR ADCs utilizing the TI method. The outcomes demonstrate that the ADC delivers a Signal-to-Noise and Distortion Ratio (SNDR) of 65.58 dB and a Spurious-Free Dynamic Range (SFDR) of 72.12 dB at a 1-GS/s sampling rate without calibration, and 69.02 dB SNDR and 81.26 dB SFDR at the same 1-GS/s sampling rate with calibration. The core layout occupies an area of 0.6 mm2 and consumes 225.02 mW of power.

A 5.8-GHz Phased Array FMCW Doppler Radar Front End for Object Localization and Movement Tracking in 65-nm CMOS

This article presents a fully integrated phased array frequency-modulated continuous-wave (FMCW) Doppler radar in 65-nm CMOS for noncontact object localization and movement tracking. The core 5.8-GHz sensor chip with the size of 2.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1.5 mm provides a peak homodyne structure receiver (RX) array gain of 47 dB and a maximum effective isotropic radiated power (EIRP) of 26 dBm on the transmitter (TX) array output with a maximum FMCW bandwidth of 275 MHz. Two <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4$</tex-math> </inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4$</tex-math> </inline-formula> antenna arrays have been implemented for RX and TX units, respectively, utilizing patch antenna elements each with a gain of 8 dBi. The phased array transceiver radar system achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm{50}^{\circ}$</tex-math> </inline-formula> beam-scanning coverage and object localization from 0.5 up to 6 m away, with movement tracking.

A Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 22-nm CMOS

This paper presents a low noise, and high linearity reconfigurable receiver (RX) analog baseband (ABB) with tunable bandwidth (BW) and gain for multi-standard applications. The designed ABB consists of a programmable gain amplifier (PGA) and a second-order active RC low-pass filter (LPF) with cutoff frequency range from 0.7 MHz–10 MHz, whereas the gain could be tuned between 0 dB and 49 dB. The proposed ABB is implemented in 22 nm CMOS process. The post-simulation results show that the current consumption is 3.36 mA from 1 V supply and the area occupies 571×328 μm 2. The ABB achieves 42.8 dBm in-band third-order harmonic intercept point (IIP3). The spurious-free dynamic range (SFDR) and in-band total harmonic distortion (THD) is 83.2 dBc and is -83.1 dB, respectively. The input referred in-band integrated noise (IRN) is 144.8 μVrms . A digital DCOC is used to calibrate the output DC level.

A 2.5 pJ/bit PVT-Tolerant True Random Number Generator Based on Native-NMOS-Regulated Ring Oscillator

In this brief, an energy-efficient true random number generator (TRNG) is presented based on the jitter noise of a single ring oscillator (RO). By XORing two different oscillation stages of the RO, consecutive pulses can be generated due to the fixed intrinsic propagation delay and more importantly, the time-varying jitter-noise-caused variation to the above delay. By continuously quantizing the above pulses’ width using another high-frequency RO-based time-to-digital converter (TDC), the TDC’s least significant bits (LSBs) are dominated by the jitter noise, of which the magnitude can be largely increased through reducing the RO’s supply voltage with a native NMOS transistor. Based on a 40-nm standard CMOS process, the proposed TRNG design is fabricated and extensively characterized. By passing the widely-exploited test tools of National Institute of Standards and Technology (NIST) and autocorrelation function, the proposed TRNG’s randomness has been well validated. Moreover, the randomness evaluation is further extended to various process-voltage-temperature (PVT) conditions, and the measured Shannon entropy is always larger than 0.999995, showing excellent PVT tolerance. Finally, the proposed TRNG features a high energy efficiency of 2.5 pJ/bit at a throughput of 53 Mbps.

A High-PCE Range-Extension CMOS Rectifier Employing Advanced Topology Amalgamation Technique for Ambient RF Energy Harvesting

This paper presents a cross-coupled CMOS rectifier for ambient RF energy harvesting, which utilizes an advanced topology amalgamation technique to significantly improve the rectifier’s power conversion efficiency (PCE) and power dynamic range (PDR), also known as the high-PCE range. Our novel technique involves adaptively self-biasing the rectifying PMOS in the last stage of the proposed rectifier, which deactivates the cross-coupled counterpart and enables the subsequent diode-based rectifier circuitry to operate efficiently during high-power operation and extends the high-PCE range by mitigating the leakage current. Fabricated in a 65-nm CMOS process, our proposed rectifier scores a wide PDR of 21 dB at 900 MHz and 15 dB at 1.8 GHz with a peak PCE of 79.77% and 51.3%, respectively, under a 100-kΩ load. Moreover, we perform a Monte Carlo simulation to showcase the impact of transistor variations. Our proposed rectifier, which offers the widest PDR compared to recently-reported designs operating at a similar frequency, is highly adaptable to the varying RF environment, enabling efficient and reliable energy harvesting for Internet of Things devices.

A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory

The need for approximate rather than exact search arises in numerous compare-intensive applications, from networking to computational genomics. This brief presents a novel sensing approach for approximate matching content-addressable memory (CAM) designed to handle large Hamming distances (HDs) between the query pattern and stored data. The proposed matchline sensing scheme (MLSS) employs a replica mechanism and a 12-transistor positive feedback sense amplifier to effectively resolve the approximate match operation. The MLSS was integrated into a 4kB approximate CAM array and fabricated in a 65nm CMOS technology. With an overall area footprint of 0.0048mm, which includes 512 sense amplifiers and the replica mechanism, the MLSS allows a flexible and dynamic adjustment of the HD tolerance threshold via several design variables. Experimental measurements demonstrate the efficiency of our sensing scheme in tolerating very large HDs with the highest sensitivity.

An Ultra-Low Power Reconfigurable Biomedical AI Processor With Adaptive Learning for Versatile Wearable Intelligent Health Monitoring.

Wearable intelligent health monitoring devices with on-device biomedical AI processor can be used to detect the abnormity in users' biomedical signals (e.g., ECG arrythmia classification, EEG-based seizure detection). This requires ultra-low power and reconfigurable biomedical AI processor to support battery-supplied wearable devices and versatile intelligent health monitoring applications while achieving high classification accuracy. However, existing designs have issues in meeting one or more of the above requirements. In this work, a reconfigurable biomedical AI processor (named BioAIP) is proposed, mainly featuring: 1) a reconfigurable biomedical AI processing architecture to support versatile biomedical AI processing. 2) an event-driven biomedical AI processing architecture with approximate data compression to reduce the power consumption. 3) an AI-based adaptive-learning architecture to address patient-to-patient variation and improve the classification accuracy. The design has been implemented and fabricated using a 65nm CMOS process technology. It has been demonstrated with three typical biomedical AI applications, including ECG arrythmia classification, EEG-based seizure detection and EMG-based hand gesture recognition. Compared with the state-of-the-art designs optimized for single biomedical AI tasks, the BioAIP achieves the lowest energy per classification among the designs with similar accuracy, while supporting various biomedical AI tasks.

A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique

This article introduces a compact and low phase noise (PN) 19-GHz quad-core class-F voltage-controlled oscillator (VCO) based on a square-geometry transformer tank using the inductor-sharing technique. The proposed square-geometry transformer tank is inherently more compact than the prevalent topologies such as star geometry, dual-row geometry, and circular geometry. The inductor-sharing technique is introduced to merge neighboring inductors into smaller ones, which further reduces the chip area. Moreover, the proposed quad-core topology supports impedance boosting at harmonic frequencies without extra chip area consumption and class-F operation is adopted to achieve better PN performance. The quad-core VCO prototype is designed and fabricated in a 65-nm CMOS process. Measured performances are 17.6 to 19.4 GHz frequency range with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 137.2 dBc/Hz minimum PN at 10 MHz offset from 19 GHz carrier with 46 mW power consumption and 0.9-V supply, resulting a figure of merit (FoM) of 186.1 dBc/Hz. Thanks to the proposed square-geometry and inductor sharing technique, the proposed VCO is the smallest in quad-core VCOs with a similar operating frequency with a core chip area of 0.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.3 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and the corresponding FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{A}}$</tex-math> </inline-formula> is 196.5 dBc/Hz.

A Quick Startup Low-Power Hybrid Crystal Oscillator for IoT Applications

In this paper, we propose a hybrid crystal oscillator which achieves both quick startup and low steady-state power consumption. At startup, a large negative resistance is realized by configuring a Pierce oscillating circuit with a multi-stage inverter amplifier, resulting in high-speed startup. During steady-state oscillation, the oscillator is reconfigured as a class-C complementary Colpitts circuit for low power consumption and low phase noise. Prototype chips were fabricated in 65nm CMOS process technology. With Pierce-type configuration, the measured startup time and startup energy of the oscillator are reduced to 1/11 and 1/5, respectively, compared with the one without Pierce-type configuration. The power consumption during steady oscillation is 30 μW.

Dead-Zone Free, Static Phase Offset Improvement Phase Detector for High Resolution and Low Jitter Delay-Locked Loop

This work presents a phase detector (PD) having dead-zone free and static phase offset improvement performance. The proposed phase detector inherits the low power consumption advantage of the conventional phase detector using two true-single-phase clocking (TSPC) DFFs. It also effectively reduces the static phase offset, even in the presence of inevitable charge pump current mismatch. And the dead-zone problem of conventional TSPC PD is overcome by using a falling edge delay inverter. The PD is implemented using a standard 180nm CMOS technology. The dimension of the PD’s layout is 11μm×16μm. Post-layout simulation shows that the power consumption is 53.8μW at 250MHz and 160μW at 800MHz. It achieves tiny static phase offset even if the charge pump has a 3.8% current mismatch.