4H-SiC Metal Semiconductor Field Effect Research Articles

Improved 4H–SiC MESFET with recessed and multi-concentration doped channel

In this paper, the 4H–SiC metal semiconductor field effect transistor with symmetric lightly doped drain (SLDD-MESFET) is improved and a 4H–SiC MESFET with recessed and multi-concentration doped channel (RMDC-MESFET) is proposed. According to the 2-D simulation results, it is found that compared with the SLDD structure, the saturation current of RMDC-MESFET is increased from 373 mA/mm to 480 mA/mm, which is 29% higher. The breakdown voltage remains stable, resulting in a 25% increase in maximum output power density, from 5.89 W/mm to 7.34 W/mm. At the same time, the transconductance of the proposed structure is increased by 28% from 68 mS/mm to 87 mS/mm, resulting in an 18% increase in the cut-off frequency from 21.45 GHz to 25.3 GHz. The DC and RF performances of the RMDC-MESFET are improved simultaneously, so the structure has good prospects for high-power and RF applications.

Improved 4H-SiC Metal–Semiconductor Field-Effect Transistors with Double-Symmetric-Step Buried Oxide Layer for High-Energy-Efficiency Applications

Improved 4H-SiC Metal–Semiconductor Field-Effect Transistors with Double-Symmetric-Step Buried Oxide Layer for High-Energy-Efficiency Applications

Improved 4H–SiC MESFET with bulgy channel

This paper proposes an improved 4H–SiC metal semiconductor field effect transistor with a bulgy channel (BC-MESFET) whose gate-source and gate-drain drift regions are shifted downward 0.1 μm relative to the channel below the gate. By introducing recesses at both ends of the metal gate, both the DC and AC characteristics of the structure have been greatly improved. The simulation results show that the saturation current of BC-MESFET is 30% higher than that of DR-MESFET, and the breakdown voltage is 78% higher. Therefore, the maximum output power density has a significant increase of 137%. In terms of RF, since the gate-source capacitance of the BC-MESFET structure is 31% lower than that of the DR-MESFET, its characteristic frequency is also improved by 18%. In this paper, aiming at high power added efficiency (PAE), the bump height H of the buffer layer under the lower gate is optimized, and a structure with 25% higher PAE than DR-MESFET is obtained.

A novel 4H–SiC MESFET with P-type doping zone and recessed buffer layer

Based on the double recessed 4H–SiC metal semiconductor field effect transistor (DR-MESFET) structure, a new 4H–SiC MESFET with p-type doping zone in drain drift region and recessed buffer layer under the source drift region (PDRB-MESFET) is proposed in this paper. The simulation results show that the breakdown voltage of this novel structure is improved by 63.76% compared with that of DR-MESFET. Thus, the maximum output power density of the device is increased by 72.85%. As for RF, the cutoff frequency decreases by 4.42% due to the increase of gate source capacitance, and RF performance deteriorates slightly. But in general, it is meaningful to exchange a slight decline in RF performance for a significant improvement in DC performance. The length and width of the p-type doping region are optimized and the optimal size of the p-type doping region is obtained.

Improved DRUS 4H-SiC MESFET with High Power Added Efficiency.

A 4H-SiC metal semiconductor field effect transistor (MESFET) with layered doping and undoped space regions (LDUS-MESFET) is proposed and simulated by ADS and ISE-TCAD software in this paper. The structure (LDUS-MESFET) introduced layered doping under the lower gate of the channel, while optimizing the thickness of the undoped region. Compared with the double-recessed 4H-SiC MESFET with partly undoped space region (DRUS-MESFET), the power added efficiency of the LDUS-MESFET is increased by 85.8%, and the saturation current is increased by 27.4%. Although the breakdown voltage of the device has decreased, the decrease is within an acceptable range. Meanwhile, the LDUS-MESFET has a smaller gate-source capacitance and a large transconductance. Therefore, the LDUS-MESFET can better balance DC and AC characteristics and improve power added efficiency (PAE).

Silicon Carbide MESFET High Frequency Oscillator for Microwave Applications

The Gouriet oscillator is mainly dealing with 4H-SiC metal semiconductor field effect transistor is fabricated with HPSI substrate and passive integrated elements are based on design for demand of the required function of frequency 1GHz. This high frequency or temperature oscillator is operated from 30 to 200˚C, the gain of the delivered power of 21.8dbm at the frequency of 1GHz and the temperature of 200˚C. The oscillator transistor output response is at 200˚C, the improved percentage is 15%. This output response of the difference in between the frequency around the vary of temperature is less than 0.5%.

An Improved 4H-SiC MESFET with a Partially Low Doped Channel.

An improved 4H-SiC metal semiconductor field effect transistor (MESFET) based on the double-recessed MESFET (DR-MESFET) for high power added efficiency (PAE) is designed and simulated in this paper and its mechanism is explored by co-simulation of ADS and ISE-TCAD software. This structure has a partially low doped channel (PLDC) under the gate, which increases the PAE of the device by decreasing the absolute value of the threshold voltage (Vt), gate-source capacitance (Cgs) and saturation current (Id). The simulated results show that with the increase of H, the PAE of the device increases and then decreases when the value of NPLDC is low enough. The doping concentration and thickness of the PLDC are respectively optimized to be NPLDC = 1 × 1015 cm−3 and H = 0.15 μm to obtain the best PAE. The maximum PAE obtained from the PLDC-MESFET is 43.67%, while the PAE of the DR-MESFET is 23.43%; the optimized PAE is increased by 86.38%.

Improved MRD 4H-SiC MESFET with High Power Added Efficiency.

An improved multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (IMRD 4H-SiC MESFET) with high power added efficiency is proposed and studied by co-simulation of advanced design system (ADS) and technology computer aided design (TCAD) Sentaurus software in this paper. Based on multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (MRD 4H-SiC MESFET), the recessed area of MRD MESFET on both sides of the gate is optimized, the direct current (DC), radio frequency (RF) parameters and efficiency of the device is balanced, and the IMRD MESFET with a best power-added efficiency (PAE) is finally obtained. The results show that the PAE of the IMRD MESFET is 68.33%, which is 28.66% higher than the MRD MESFET, and DC and RF performance have not dropped significantly. Compared with the MRD MESFET, the IMRD MESFET has a broader prospect in the field of microwave radio frequency.

Modeling of Drain Induced Barrier Lowering Effect for Bi-Material Buffer Gate 4H-SiC Metal Semiconductor Field Effect Transistor

A novel bi-material buffer gate 4H-SiC metal semiconductor field effect transistor (BMGFET) is proposed for the purpose of restraining the drain-induced barrier lowering (DIBL) effect. The analytical model of the DIBL effect for the BMGFET is built and its occurrence degree is evaluated by analyzing the dependence of the threshold voltage shift and the sub-threshold slope factor on the drain bias and the structure parameters. The results reveal that the DIBL effect is significantly suppressed because there appears a valley in the graph of the potential distribution function of the BMG structure.

An Improved UU-MESFET with High Power Added Efficiency.

An improved ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (IUU-MESFET) is proposed in this paper. The structure is obtained by modifying the ultrahigh upper gate height h of the ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (UU-MESFET) structure, and the h is 0.1 μm and 0.2 μm for the IUU-MESFET and UU-MESFET, respectively. Compared with the UU-MESFET, the IUU-MESFET structure has a greater threshold voltage and trans-conductance, and smaller breakdown voltage and saturation drain current, and when the ultrahigh upper gate height h is 0.1 μm, the relationship between these parameters is balanced, so as to solve the contradictory relationship that these parameters cannot be improved simultaneously. Therefore, the power added efficiency (PAE) of the IUU-MESFET structure is increased from 60.16% to 70.99% compared with the UU-MESFET, and advanced by 18%.

A novel 4H-SiC MESFET with multi-recessed p-buffer layer for high energy-efficiency applications

In this paper, a novel structure named 4H-SiC metal semiconductor field effect transistor with multi-recessed p-buffer layer named MRB MESFET is proposed and simulated. The design of the new structure takes the power added efficiency into account to reduce energy consumption. The channel is assisted to deplete further and the electric field in the drift region for the new structure is modulated by utilizing a multi-recessed p-buffer layer. Thus, the superior gate-source capacitance is obtained and the larger saturation drain current and breakdown voltage are achieved compared with the double-recessed p-buffer layer structure named DRB MESFET. The simulated results demonstrate that the breakdown voltage and the saturation drain current of the MRB MESFET are about 57.89% and 5.63% greater than that of the DRB MESFET. There is an improvement of 86.5% in the maximum output power density for the proposed structure compared with that of the DRB MESFET when the both RF characteristics are similar to. The related structure parameters m = 0.10 μm, n = 0.20 μm are optimized at the beneficial maximum output power density (Pmax), cut-off frequency (fT) and power added efficiency (PAE). All the results show that the advantages and the potential capacities of the MRB MESFET are greater than the DRB MESFET.

A novel 4H-SiC MESFET with serpentine channel for high power and high frequency applications

In this paper, a novel 4H-SiC metal semiconductor field effect transistor with serpentine channel (SC-MESFET) is proposed which the gate-drain drift region shifts downward integrally compared to the gate-source drift region. With the depth of the gate-drain shift increasing, the channel electric field and the gate depletion layer have been modulated. The simulated results show that the drain saturation current and breakdown voltage of the SC-MESFET are about 21.5% and 46.7% larger than that of the conventional double-recessed 4H-SiC MESFET (DR-MESFET). The gate-source capacitance of proposed structure is also improved from 0.59 pF/mm to 0.51 pF/mm and the DC transconductance of the SC-MESFET is very close to that of the DR-MESFET at the bias conditions of Vgs = 0 V and Vds = 40 V, which results in better RF characteristics. All of the results show that the novel 4H-SiC MESFET with serpentine channel has superior electrical characteristics and performances.

A novel 4H-SiC MESFET with double upper gate and recessed p-buffer

A novel structure named 4H-SiC metal semiconductor field effect transistor with double upper gate and recessed p-buffer (DURP MESFET) is proposed and simulated in this paper. The increase in the saturation drain current and the breakdown voltage, and the decrease in the gate-source capacitance are achieved compared with those of DR MESFET, which are result from the reduction of the depletion region under the gate by the introduction of a double upper gate. The negative influence of the double upper gate on trans-conductance is suppressed by employing a recessed p-buffer. With the optimal size, the height of the upper gate Z = 0.10 μm, the depth and width of the recessed p-buffer of 0.05 μm and 0.35 μm, superior DC and RF characteristics for the proposed structure can be obtained, such as a 22.5% increase in the saturation drain current and a 17.9% increase in the breakdown voltage compared to the DR MESFET. The gate-source capacitance is 0.439 pF/mm compared to 0.573 pF/mm of DR MESFET by reference to simulated results, which would lead to the DURP MESFET has excellent RF performance.

Improved multi-recessed 4H–SiC MESFETs with double-recessed p-buffer layer

An improved multi-recessed 4H–SiC metal semiconductor field effect transistor (MRD-MESFET) with double-recessed p-buffer layer (DRB-MESFET) is proposed in this paper. By introducing a double-recessed p-buffer layer, the gate depletion layer is further modulated, and higher drain saturation current and DC transconductance are obtained compared with the MRD-MESFET. The simulations show that the drain saturation current of the DRB-MESFET is about 42.4% larger than that of the MRD-MESFET. The DC transconductance of the DRB-MESFET is almost 15% higher than that of the MRD-MESFET and very close to that of double-recessed structure (DR-MESFET) at the bias conditions of Vgs=0V and Vds=40V. The proposed structure has an improvement of 26.1% and 74.2% in the output maximum power density compared with that of the MRD-MESFET and DR-MESFET, respectively. In the meanwhile, the proposed structure possesses smaller gate-source capacitance, which results in better RF characteristics.

A novel 4H-SiC MESFET with ultrahigh upper gate

A novel 4H-SiC metal semiconductor field effect transistor with ultrahigh upper gate (UU-MESFET) by depletion layer variation and electric field modulation is proposed in this paper for the first time. The prominent merits in the proposed structure are the smaller gate depletion layer and the higher electric field peak produced by the electric field modulation due to ultrahigh upper gate. A higher electric field peak is introduced by ultrahigh upper gate at lower gate corner instead of upper gate corner, which leads to electric field breakdown. Using ISE simulation, the breakdown voltage of the UU-MESFET is improved by 55% and the drain saturation current is increased by 15% than those of the conventional DR-MESFET, which means that the UU-MESFET has an improvement of about 78% in the maximum output power density compared to the DR-MESFET. Furthermore, the gate–source capacitance of the proposed structure is about 17% smaller than that of the DR-MESFET. Therefore the proposed structure has fantastic DC performance and in the meanwhile possesses better RF characteristics.

A novel 4H–SiC MESFET with clival gate

In this paper, a novel 4H–SiC metal semiconductor field effect transistor (MESFET) with a clival gate structure (CG-MESFET) is proposed. The drain current (ID) and the breakdown voltage (VB) are simulated and compared to the traditional double-recessed gate 4H–SiC MESFET (DR-MESFET). The results indicate that the drain current (ID) of the CG-MESFET transforms with the change of end point of clival gate (EPCG), and it reaches to a maximum value about 545mA when EPCG is at 1/2 of whole gate, thus, the drain current (ID) has a much greater increase than that of the DR-MESFET. The CG-MESFET has the advantages of high breakdown voltage (VB) that is increased by 15% and superior DC performances over the DR-MESFET.

An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

An improved analytical model for the current—voltage (I–V) characteristics of the 4H-SiC metal semiconductor field effect transistor (MESFET) on a high purity semi-insulating (HPSI) substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation. The analytical model is used to exhibit DC I–V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations (Silvaco®-TCAD). The proposed model also illustrates the effectiveness of the gate—source distance scaling effect compared to the gate—drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I–V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

Dependence of the Breakdown Voltage of 4H-SiC MESFET’s on the Field Plate and Step-Channel

The breakdown mechanism of the 4H-SiC metal-semiconductor field effect transistor (4H-SiC MESFET) at a large drain bias is explored and the dependence of breakdown voltage on the field-plate and the step-channel is investigated by simulation. The results revealed that the breakdown occurs at the corner of the gate near to the drain. The channel step and the field-plate length have sensitive effect on the breakdown voltage. The breakdown characteristics are improved since the electric field peak is lowered at breakdown point in the step-channel and field-plate structures. The largest breakdown voltage can be achieved by optimizing the field-plate length.

The Role of Substrate Compensation on DC Characteristics of 4H-SiC MESFET with Buffer Layer: A Combined Two-Dimensional Simulations and Analytical Study

An analytical model of 4H-SiC metal semiconductor field effect transistor (MESFET) is proposed with buffer layer on high purity semi-insulating (HPSI) 4H-SiC substrate compensated by multiple deep level traps. The contribution of deep level traps (DLT) is projected and verified using two-dimensional simulations (Silvaco®). The modeled DC characteristics are compared with two-dimensional simulations performed on the same device as considered in the analytical model.The 4H-SiC MESFET is simulated with and without the effect of buffer layer and the electron concentration profiles in different regions are observed from two-dimensional simulations.The electron concentration profiles obtained at channel-substrate interface clearly shows that when the buffer layer is not present, the channel electrons get trapped by the deep level traps used for substrate compensation. It is also observed that the inclusion of buffer layer minimizes the extent of electron trapping by screening out the active channel from the substrate. However, the trapping phenomena take place in both the cases.We believe that the proposed model of 4H-SiC MESFET which includes the substrate compensation through multiple deep level traps may be useful for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

A novel double-recessed 4H-SiC MESFET using scattering the electric field for high power and RF applications

In this paper, we present the unique features exhibited by a novel double-recessed 4H-SiC Metal–Semiconductor Field Effect Transistor (MESFET) in which the channel consists of a floating metal region (FMR-MESFET). The key idea in this work is to scatter the electric field lines and modify the ionization mechanism. The floating metal region allows more electrons participate in carrying current, so the optimized results show that the breakdown voltage (VBR) and the drain saturation current (IDsat) increase about 54% and 22% compared with a conventional double recessed MESFET (CDR-MESFET), respectively. Therefore the maximum output power density (Pmax) improved by factor 3.38 in comparisons with conventional one. Also, the cut-off frequency (fT) of 15GHz and the maximum oscillation frequency (fMax) of 135GHz for 4H-SiC FMR-MESFET is obtained compared to 13GHz and 120GHz for that of the CDR-MESFET and the minimum figure noise (Fmin) decreased as a result of reducing gate–drain and gate–source capacitances by about 42% and 40%, respectively. Therefore, the FMR-MESFET has superior RF frequency and high electrical performances.