4H-SiC Insulated Gate Bipolar Transistors Research Articles

A novel 4H–SiC IGBT with double gate PMOS for improving the switch controllability and FBSOA

In this work, a 4H–SiC insulated-gate bipolar transistor (IGBT) with double gate PMOS (DGPMOS) is proposed. In the on-state, DGPMOS IGBT can form a hole barrier, thus reducing the on-state voltage (VON). During the turn-on and turn-off transients, DGPMOS IGBT can form the extra hole extraction paths. This helps to reduce the turn-off loss (Eoff) and the gate displacement current (IG_dis). The simulation results show that compared with GS IGBT, the VON of DGPMOS IGBT is decreased by 58.04% under the same Eoff. Compared with PMOS IGBT, DGPMOS IGBT achieves better controllability in turn-on dIC/dt and peak turn-on current (Imax). At the same turn-on loss (Eon), the maximum reverse recovery dVKA/dt is lowered by 26.67%, and the electromagnetic interference (EMI) noise is suppressed. In addition, because DGPMOS IGBT has a small saturation current density (Jsat), its forward bias safe operating area (FBSOA) is greatly improved.

10kV+ Rated SiC n-IGBTs: Novel Collector-Side Design Approach Breaking the Trade-Off between dV/dt and Device Efficiency

10kV+ rated 4H- Silicon Carbide (SiC) Insulated Gate Bipolar Transistors (IGBTs) have the potential to become the devices of choice in future Medium Voltage (MV) and High Voltage (HV) power converters. However, one significant performance concern of SiC IGBTs is the extremely fast collector voltage rise (dV/dt) observed during inductive turn-off. Studies on the physical mechanisms of high dV/dt in 4H-SiC IGBTs revealed the importance of collector-side design in controlling the phenomenon. In this paper we propose a novel collector-side design approach, which consists of four n-type layers with optimized doping densities and allows the control of dV/dt independently from the device performance. Further, we demonstrate a reduction of dV/dt by 87% without degrading the high switching frequency capability of the device, or the on-state performance, through the addition of two n-type epitaxial layers in the collector side, between the buffer and the drift regions.

Thin-drift-layer n-channel 4H-SiC IGBT with low switching loss and switching ringing reduction

An n-channel 4H-SiC insulated-gate bipolar transistor (IGBT) with an extremely low switching loss was demonstrated by making 70 μm thin drift layers designed for 6.5 kV blocking voltage, without substrates. A conductivity-modulated bipolar operation was successfully performed as a on-voltage of 4.96 V at a 100 A cm−2 collector current. The turn-off losses under 3.6 kV/32 A operation were 8.8 (at room temperature) and 22.7 mJ (at 150 °C), which were much lower than the estimated losses of SiC IGBTs with thick drift layers. A detailed investigation on turn-off transition of SiC IGBTs specifically focused on a voltage-slope increase was also conducted. This phenomenon can cause ringing in switching characteristics. A device structure has been proposed to eliminate it by controlling the expansion of a depletion layer. Voltage-slope control and ringing reduction without noticeable degradation in static characteristics and switching loss were demonstrated with the SiC IGBT with the proposed device structure.

Physical modeling and design optimization of 4H-SiC insulated gate bipolar transistors for dv/dt reduction

The extremely high dv/dt of 4H-SiC insulated gate bipolar transistor (IGBT) becomes the major concern in its next-generation large-volume power conversion applications because severe electromagnetic interference (EMI) is induced. However, the root reason for its high dv/dt and the method of suppressing EMI have not been extensively investigated yet. In this paper, we proposed a novel physical model for SiC IGBT to identify the major limiting device design parameters of dv/dt during switching transients. The influences of SiC IGBT’s design parameters on its dv/dt and power dissipation are quantitatively analyzed by means of the physical model. Comparisons between the theoretical predictions and technology computer-aided design simulation results validate the physical model. The results on design optimization of a 18 kV n-channel SiC IGBT shows that 80% reduction of dv/dt and 60% reduction in turn-off power dissipation are achieved simultaneously without sacrificing its forward voltage drop.

Low Turn-Off Loss 4H-SiC Insulated Gate Bipolar Transistor With a Trench Heterojunction Collector

In this work, an improved 4H-SiC insulated gate bipolar transistor (IGBT), or CTH-IGBT, with a trench p-polySi/p-SiC heterojunction on the backside of the device is proposed to reduce the turn-off energy loss ( $E_{off}$ ) and turn-off time ( $T_{off}$ ). The electrical properties of the proposed and contrast structures are all simulated using the ATLAS simulation software to research the working mechanism of this improved structure. For the static performance, the specific ON-resistance ( $R_{on,sp}$ ) and the figure of merit ( ${\mathrm{ FOM}} = V_{BR}^{2}/ R_{on,sp}$ ) are not influenced much as compared to the traditional structure at the same breakdown voltage ( $V_{BR}$ ) of 12 kV. However, with a prominent electron current path formed by the heterojunction region of CTH-IGBT, a very available conduction path to discharge the electrons during turn-off process is proved in this article. The simulation results demonstrate that compared with the traditional structure, the turn-off energy loss of the CTH-IGBT is reduced by 76.4%, while the turn-off time is reduced by 85.0%.

Enhanced Miller plateau characteristics of a 4H-SiC insulated-gate bipolar transistor in the presence of interface traps

Miller plateau characteristics of a 4H-SiC insulated-gate bipolar transistor (IGBT) is investigated during a gate voltage turn-on under the presence of interface carrier traps at the MOSFET gate oxide. The plateau, which is observed in the device gate-emitter voltage, increased with respect to both height and length. The plateau height is mainly determined by the density increase of trap states, which also causes slow charging of the gate capacitance in the overlap region that results in a longer plateau length. The shallow trap states contribute mainly to the plateau increase. It is observed that the switching loss at turn-on can increase by more than 60% due mainly to the carrier traps at the shallow trap states.

Investigation of 4H-SiC insulated-gate bipolar transistor turn-off performance for achieving low power loss

The dynamic characteristics of a 4H-SiC insulated-gate bipolar transistor (IGBT) at pulse switching is investigated by incorporating reported measurements of the interface defect density to device simulation. Different trap features such as energy states and trap time constants are investigated to determine the influence of traps on circuit performance. The capture cross-section parameter used in the simulation depicts the probability of traps to trap/detrap carriers which relates to the carrier trap time constant. It is demonstrated that trapped carriers from the on-state condition cause enhanced generation current during the off-state condition, which give rise to undesired leakage current in addition to the threshold voltage shift previously reported. The device power dissipation is increased by a factor of 100 due to the defects.

Switching characteristics of a 4H-SiC insulated-gate bipolar transistor with interface defects up to the nonquasi-static regime

The switching characteristics of a trench-type 4H-SiC insulated-gate bipolar transistor (IGBT) device with interface defects are analyzed up to the nonquasi-static (NQS) switching regime using reported interface density measurements and device simulation. Collector current degradation characterized by threshold voltage shift to higher gate voltages and reduction of current magnitude due to carrier trapping are observed under quasi-static (QS) simulation condition. At slow switching of the gate voltage, carrier trapping causes a hump in the transient current at the start of conduction. At very fast switching, the current hump is limited by the NQS effect which results to a reduced switching efficiency and increased on-resistance.

Modeling of SiC IGBT Turn-Off Behavior Valid for Over 5-kV Circuit Simulation

This paper presents a compact model of SiC insulated-gate bipolar transistors (IGBTs) for power electronic circuit simulation. Here, we focus on the modeling of important specific features in the turn-off characteristics of the 4H-SiC IGBT, which are investigated with a 2-D device simulator, at supply voltages higher than 5 kV. These features are found to originate from the punch-through effect of the SiC IGBT. Thus, they are modeled based on the carrier distribution change caused by punch through and implemented into the silicon IGBT model named “HiSIM-IGBT” to obtain a practically useful SiC-IGBT model. The developed compact SiC-IGBT model for circuit simulation is verified with the 2-D device simulation data.

On the Assessment of Temperature Dependence of 10 - 20 kV 4H-SiC IGBTs Using TCAD

This paper addresses and evaluates the temperature dependence performance of silicon carbide (4H-SiC) based insulated gate bipolar transistors (IGBTs) using two dimensional numerical computer aided design tool (i.e., Atlas TCAD from Silvaco). Using identical set of device physical parameters (doping, thicknesses), simulated structure was first caliberated with the experimental data. A minority carrier life time in the drift layer of 1.0 – 1.6 µs and contact resistivity of 0.5 - 1.0 x 10-4 Ω-cm2 produces a close match with the experimental device. A set of n type IGBT structures were then numerically simulated to extract the conduction losses for various blocking voltage classes. An on-resistance first decays with temperature (i.e., increased in ionization level, and increase in minority carrier life time), stays nearly constant with further increase in the temperature (may be all carriers are now fully ionized and increase in carrier life time is compensated with decrease in the carrier mobility) and finally increases linearly with temperature (>450 oC) due to decrease in the carrier mobility. Compared with Si based IGBTs, numerical simulation predicts lower VCEON and RON values for 4H-SiC based IGBTs for higher voltage classes and hence potential for achieving smaller conduction losses for SiC based IGBTs.

Design and Characterization of High-Voltage 4H-SiC p-IGBTs

High-voltage p-channel 4H-SiC insulated gate bipolar transistors (IGBTs) have been fabricated and characterized. The devices have a forward voltage drop of 7.2 V at 100 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a -16 V gate bias at 25degC, corresponding to a specific on-resistance of 72 mOmega ldr cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a differential on-resistance of 26 mmOmega ldr cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Hole mobility of 12 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V ldr s in the inversion channel with a threshold voltage of -6 V was achieved by optimizing the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> well doping profile and gate oxidation process. A novel current enhancement layer was adopted to reduce the JFET resistance and enhance conductivity modulation by improving hole current spreading and suppressing the electron current conduction through the top n-p-n transistor. Inductive switching results have shown that the p-IGBT exhibited a turn-off time of ~1 mus and a turn-off energy loss of 12 m J at 4-kV dc-link voltage and 6-A load current at 25degC. The turn-off trajectory from the measured inductive load switching waveforms and numerical simulations shows that the p-IGBT had a near-square reverse bias safe operating area. Numerical simulations have been conducted to achieve an improved tradeoff between forward voltage drop and switching off energy by investigating the effects of drift layer lifetime and p-buffer layer parameters. The advantages of SiC p-IGBTs, such as the potential of very low ON-state resistance, slightly positive temperature coefficient, high switching speed, small switching losses, and large safe operating area, make them suitable and attractive for high-power high-frequency applications.

Comparison of High-Voltage 4H-SiC Insulated-Gate Bipolar Transistor (IGBT) and MOS-Gated Bipolar Transistor (MGT)

In this paper, the performance of high-voltage (10kV) 4H-SiC n- and p-channel IGBTs and n-channel MOS-Gated Bipolar Transistor (MGT) are investigated and compared using 2- dimensional numerical simulations. We have found that the MGT in SiC is not suitable for applications at high blocking voltages and the p-channel IGBT is a better choice because of a much higher conductivity modulation in the drift region.