3D Integration Technology Research Articles

Atomic-scale insights into the microstructure and interface evolution mechanism of copper/tantalum nanofilms during ultra-precision grinding

The copper (Cu)/tantalum (Ta) nanofilms are the vital component in the through silicon via (TSV) wafer. However, the current lack of research on the ultra-precision machining of Cu/Ta nanofilms limits the development of TSV-based 3D integration technologies. In this work, molecular dynamics simulations are conducted to reveal the microstructure and interface evolution mechanism of Cu/Ta nanofilms during nano-grinding under various grinding depths. The results show that the material removal mode differs between the Cu and Ta layers, and the thickness of the subsurface damage layer of the Cu layer is greater than that of the Ta layer. The Cu/Ta interface is well stabilized, and small amounts of micro-defects appear only at larger grinding depths after grinding. The lattice mismatch of the constituent layers and the hindering role by the interface lead to stress concentration at the interface, and it is more obvious with increasing grinding depth. Nevertheless, there is a significant stress release after grinding. Our computations indicate that the competition between the evolution of interfacial structures and discrepancies in the physical properties of constituent layers leads to an increase in grinding forces at the interface. Furthermore, the heat transfer is obstructed by the Cu/Ta interface. This study provides valuable insights into the grinding mechanisms of Cu/Ta nanofilms, which is conducive to further improving the manufacturing process of the TSV wafer and enhancing the performance of microelectronic devices.

A review of physical heat dissipation methods for 3D integrated technology

Three-dimensional integrated circuits have higher integration than two-dimensional integrated circuits, and can obtain higher performance and lower power consumption in a certain space. In order to fulfill higher efficiency, thermal management becomes particularly important in 3D integration technology. However, the traditional heat dissipation method cannot satisfy the heat dissipation needs of three-dimensional integrated circuits, which require better heat dissipation methods to be developed. This paper introduces the realization of three-dimensional integrated circuit using silicon via (TSV) technology, which allows the chip to be vertically stacked to transmit information. This paper summarizes the research methods and findings of three-dimensional integrated circuit heat dissipation in recent years, including thermal through silicon via (TTSV) and microchannel cooling. It also emphasizes the advantages and disadvantages of both mehods, and the challenges faced in current research via an overview. The future research trend for both heat dissipation methods mainly consists of combining special algorithms to achieve thermal-electrical codesign and thermal management of three-dimensional integrated circuits.

Effect of different Ba/Sr ratios on the properties of borosilicate glasses for application in 3D packaging

Borosilicate glass is a promising material for 3D system integration technology due to its high integration and adjustable CTE (coefficient of thermal expansion). However, the structure and composition of borosilicate glasses result in a relatively high melting point and dielectric loss, which hinders the wide application of such glasses. In this study, we analyze the relationship between different Ba/Sr ratios and the structure and properties of the glass. We determine and further analyze the effect of mixed alkaline earth effect on the proportion of the Qn unit, [BO3], and [SiO4] in the glass structure, and consequently, its influence on the dielectric properties. Alkaline earth metals act as network-modifying ions to reconnect the interrupted network of the glass, stabilizing the glass structure and reducing the polarization loss of the glass. Raman analysis showed that the Raman spectrum shifted towards higher frequencies as the ratio of Al2O3/RO increased, with the Raman bands at 1300 cm−1-1500 cm−1 almost disappearing, while the Raman area at 730 cm−1-830 cm−1 increased. This indicated that the [BO3] units formed a ring structure in the glass, thereby enhancing the compactness of the glass network. The thermal expansion coefficient was 4.09 ppm K−1 when the Ba/Sr ratio was 1:1, and the dielectric constant and dielectric loss were 4.3 and 1.24 × 10−3, respectively. Overall, the dielectric properties and thermal expansion coefficients of the glass can be effectively reduced by doping with alkaline-earth metals, making the borosilicate glass more suitable for three-dimensional integrated system packaging.

Fast in-line failure analysis of sub-micron-sized cracks in 3D interconnect technologies utilizing acoustic interferometry

More than Moore technology is driving semiconductor devices towards higher complexity and further miniaturization. Device miniaturization strongly impacts failure analysis (FA), since it triggers the need for non-destructive approaches with high resolution in combination with cost and time efficient execution. Conventional scanning acoustic microscopy (SAM) is an indispensable tool for failure analysis in the semiconductor industry, however resolution and penetration capabilities are strongly limited by the transducer frequency. In this work, we conduct an acoustic interferometry approach, based on a SAM-setup utilizing 100 MHz lenses and enabling not only sufficient penetration depth but also high resolution for efficient in-line FA of Through Silicon Vias (TSVs). Accompanied elastodynamic finite integration technique-based simulations, provide an in-depth understanding concerning the acoustic wave excitation and propagation. We show that the controlled excitation of surface acoustic waves extends the contingency towards the detection of nm-sized cracks, an essential accomplishment for modern FA of 3D-integration technologies.

3D packaging and Moore’s Law

Abstract This paper describes how the semiconductor industry has seen steady improvements in key metrics such as performance, power consumption, and area, but as the semiconductor industry shrinks in device size and the technical challenges of ever-increasing performance demands, it is critical to improve chip performance for maximizing the operating frequency of individual ICs and reducing their power consumption. But when talking about improving chip performance, it is important not to focus solely on the individual integrated circuit (IC), but to evaluate it as part of the overall system. For example, as microprocessor frequency increases, so does the demand for main memory data. However, if the connections between the chips that transfer data to the processor do not keep pace with the increase in performance, these connections can become a bottleneck in the performance of the entire system. Instead, this paper describes a typical architecture for semiconductor 3D integration, highlights the technology choices for 3D integration implementation, and analyzes and explains the design challenges it presents. After outlining the above, this paper also analyzes the applications and achievements of 3D integration technology in recent years.

Optimizing Ultrathin 2D Transistors for Monolithic 3D Integration: A Study on Directly Grown Nanocrystalline Interconnects and Buried Contacts.

The potential of monolithic 3D integration technology is largely dependent on the enhancement of interconnect characteristics which can lead to thinner stacks, better heat dissipation, and reduced signal delays. Carbon materials such as graphene, characterized by sp2 hybridized carbons, are promising candidates for future interconnects due to their exceptional electrical, thermal conductivity and resistance to electromigration. However, a significant challenge lies in achieving low contact resistance between extremely thin semiconductor channels and graphitic materials. To address this issue, an innovative wafer-scale synthesis approach is proposed that enables low contact resistance between dry-transferred 2D semiconductors and the as-grown nanocrystalline graphitic interconnects. A hybrid graphitic interconnect with metal doping reduces the sheet resistance by 84% compared to an equivalent thickness metal film. Furthermore, the introduction of a buried graphitic contact results in a contact resistance that is 17 times lower than that of bulk metal contacts (>40nm). Transistors with this optimal structure are used to successfully demonstrate a simple logic function. The thickness of active layer is maintained within sub-7nm range, encompassing both channels and contacts. The ultrathin transistor and interconnect stack developed here, characterized by a readily etchable interlayer and low parasitic resistance, leads to heterogeneous integration of future 3D integrated circuits (ICs).

Coupling effect between electromigration and joule heating on the failure of ball grid array in 3D integrated circuit technology

Ball Grid Array (BGA) packaging method has been widely used in microelectronic devices, and electromigration (EM) in BGA is a crucial reliability issue, determining the performance of the products. Herein, we report a new failure mode induced by a coupling effect of EM and Joule heating in BGA structure. The test sample consists of a roll of 500 μm-BGA solder joints with upper and lower Cu under-bump-metallization (UBM) of different thicknesses, 16 μm, and 68 μm, respectively. Open failures of the thinner cathodic Cu UBM at the contacting area with solder joint were observed under four different EM conditions (130 °C-3000 A/cm2, 160 °C-2300 A/cm2, 160 °C-3000 A/cm2, and 160 °C-4600 A/cm2). Infrared (IR) results reveal the temperature at the thinner Cu UBM is higher than that in the solder joint as well as at the thicker Cu UBM. Simulation results elucidate the current density at the contacting area is about 22 times higher than the average density in the solder joint, so the effect of current crowding can be very serious in the failure site. Furthermore, severe current crowding and Joule heating promote the nucleation rate of voids at the joint location, which can further increase the current density and temperature, leading to a positive feedback effect until an open failure occurs in the circuitry. Our analysis enables the discussion of a coupling failure mode of EM and Joule heating in BGA, and provides a valuable guide of device design against EM failure in consumer electronic products.

High Cleanliness and High Hydrophobic/Hydrophilic Contrast Done by Direct Wafer Bonding for Die-to-Wafer Self-Assembly

Die-to-wafer assembly is a promising technology for 3D-integration in terms of yield. However, it is difficult to combine high placement accuracy and high throughput with a pick and place process. To overcome these issues, self-assembly and collective transfer for die-to-wafer were proposed [1].With the self-assembly technology, direct bonding is used for the assembly and the surface tension of liquid droplets drives the chips and precisely aligns them to predetermined assembly areas on carrier wafers. A good water containment on the bonding site is needed to ensure a precise alignment. It is controlled by two parameters: topographical and hydrophilic/hydrophobic contrast. A step of around 15 µm surrounding the bonding area plays the role of the topographical contrast. The hydrophilic/hydrophobic contrast is obtained by coating an hydrophobic organic compound around the hydrophilic bonding site. Collective transfer can be achieved when dies are simultaneously bonded onto a target wafer covered with bonding sites (see figure 1).The preparation of the target wafer as well as dies is a major topic of interest. As shown in figure 2 the direct bonding site is often defined by lithographic means: step and hydrophobic coating [2]. Extremely cleaned surfaces are required to ensure a good bonding quality. As a consequence, all particles and organic traces must be perfectly removed during the resist stripping step. It is here challenging as the organic resist must be removed while preserving the organic hydrophobic material. Highly aggressive and efficient stripping solutions cannot be used to obtain very clean bonding surfaces and an alternative process had to be developed.We propose an innovative process based on a temporary bonding protection of the bonding site for the hydrophobic coating. A typical flow is presented in figure 2. A standard photolithography and etching process is used to obtain steps at the edges of the bonding site. An efficient stripping based on plasma and wet cleaning yields a surface that is ready for bonding. This surface is bonded with another temporary wafer. The resulting stack is dipped in a solution of hydrophobic material and then dismounted.As a demonstration, 40 target bonding sites were defined onto a 200 mm diameter silicon wafer. First, a 2µm thick oxide layer was deposited. Then, bonding sites were defined by photolithography and etching. The step height was 15 µm and bonding areas 8x8 mm². This wafer was bonded to a temporary carrier. The acoustic picture of the resulting stack is provided in figure 3a): all bonding sites were correctly bonded on the carrier. The stack was then dipped in a fluorinated polymer solution. After dismounting the temporary carrier, the water contact angle of the surface was measured: it was around 10° on the bonding site and 90° on the surrounding area. A SEM image confirmed the presence of the hydrophobic polymer on the surrounding area but also on the sidewalls of steps (figure 3b).In the same way, 10x10 mm² dies with 8x8 mm² bonding sites were fabricated. A collective bonding between the target wafer and the 40 dies was performed: 10 µL droplets were deposited onto each bonding site. 70 % of dies were transferred onto the target wafer. The alignment performance was evaluated with dedicated marks on target and dies: 50 % of die were aligned with a precision below 1 µm. The stack withstood a 2h annealing at 400°C without any defect appearance. These results demonstrate the interest of the new process for the fabrication of high contrasted surfaces for self-assembly bonding while keeping a very high cleanliness of the hydrophilic bonding area.The authors acknowledge financial support from INTEL Corporation, United States[1] T. Fukushima, Proc. Int. Electron Dev. Meet., 2005, pp. 359–362.[2] A. Bond , 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2022, pp. 168-176. Figure 1

Modeling Of 3D Integrated Circuits, Heat Transfer Solutions and Application

As transistor sizes approach the quantum limit, the cost of further shrinking them becomes prohibitively high. To overcome this limitation and surpass Moore's Law, 3D (Integrated Circuits) IC technology has emerged. However, while 3D ICs offer advantages like high integration, they also present challenges related to thermal management. This paper introduces and discusses partial differential equations and modeling methods for heat transfer in 3D ICs. It explores solutions to address thermal conduction problems and analyzes the potential application areas and prospects of 3D ICs. By utilizing different modeling methods, we can optimize the heat transfer problem during the design stage. To enhance the thermal conduction of 3D ICs, this study proposes the use of copper thermal conductive materials, graphene thermal conductive layers, and phase-change material cooling. As technology advances and costs decrease, 3D ICs are expected to find broader applications in high-performance computing, artificial intelligence, the Internet of Things, and other fields. Despite its numerous advantages, 3D integrated circuit technology still faces challenges such as cost, heat, and silicon vias. To address these issues, further technological innovations and updates to Computer Aided Design (CAD) tools are necessary. Overall, this study holds significant social and scientific importance as it promotes the development of 3D IC technology, improves electronic device performance, and advances scientific research.

Research of Vertical via Based on Silicon, Ceramic and Glass.

With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore's Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed.

Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs

3D integration technology is one of the leading options to advance Moore’s Law beyond conventional scaling. One of the 3D integration choice is the heterogeneous integration with the benefits of power saving over the homogeneous integration. With the lack of commercial 3D tools, existing 3D physical design flows utilizes 2D commercial tools to perform 3D IC physical synthesis. Specifically, these flows build 2D designs first and then convert them into 3D designs. However, several works demonstrate that design qualities degrade during this 2D-3D transformation and some of the flows do not support heterogeneous integration. In this paper, we propose Snap-3D, a constraint-driven placement approach to build commercialquality 3D ICs, which supports both homogeneous and heterogeneous 3D ICs. Our key idea is based on the observation that if the standard cell height is contracted and partitioned into multiple tiers, any commercial 2D placer can place them onto the row structure and naturally achieve high-quality 3D placement. This methodology is shown to optimize power, performance, and area (PPA) metrics across different tiers simultaneously and minimize the aforementioned design quality loss. Experimental results on seven industrial designs demonstrate that Snap-3D achieves up to 10.9% wirelength, 9% power, and 25% performance improvements compared with state-of-the-art 3D design flows.

BBCube 3D Integration Technology Utilizes WOW and COW Hybrid Processes

BBCube 3D Integration Technology Utilizes WOW and COW Hybrid Processes

Fabrication and Training of 3D Conductive Polymer Networks for Neuromorphic Wetware

AbstractThe human brain possesses an exceptional information processing capability owing to the 3D and dense network architecture of numerous neurons and synapses. Brain‐inspired neuromorphic hardware can also benefit from 3D architectures, such as high integration of circuits and acquisition of highly complex dynamical systems. In this study, for future 3D neuromorphic engineering, 3D conductive polymer networks consisting of poly(3,4‐ethylenedioxy‐thiophene) doped with poly(styrene sulfonate) anions (PEDOT:PSS) are successfully and stably fabricated between multiple electrodes from scratch in precursor solution by electropolymerization. The networks efficiently emulate the 3D local connections between neighboring neurons observed in the cortex. This novel technology, which allows 3D conductive wiring only between desired electrodes, is unprecedented and has potential as an underlying technology for 3D integration. Furthermore, the experimental results also conclusively prove that conductance modification can be performed by manipulating the physical and chemical properties of 3D branch‐wired conductive polymer wires, thus demonstrating for the first time the feasibility of neuromorphic wetware with enhanced biological plausibility in the subsequent post‐Moore era.

Probing molecular structures at buried solid/solid interfaces involving low-k materials or polymers in situ nondestructively: a review

BackgroundWith the development of three-dimensional (3D) integration technology including extreme ultraviolet (EUV) lithography, more and more buried interfaces are involved in a device. It is important to probe such buried solid/solid interfaces in situ, but due to the lack of appropriate metrology, it is difficult to do so.AimThis review aims to introduce sum frequency generation (SFG) vibrational spectroscopy to researchers and engineers in the research fields related to 3D integration technology including EUV lithography. SFG can probe buried solid/solid interfaces in situ nondestructively.Review ApproachThis review presents the SFG technique and the recent results obtained from SFG studies on a variety of solid/solid interfaces, including porous low-k material/silicon interfaces, plasma treated polymer/epoxy interfaces, flux treated metal/epoxy interfaces, chemical reactions at buried solid/solid interfaces, and structures of buried solid/solid interfaces in multilayered thick device.ConclusionsSFG has been successfully applied to elucidate molecular structures and molecular interactions at buried solid/solid interfaces in situ nondestructively. SFG has great potential to probe buried interfaces in devices based on 3D integration technology.

3D integration technologies for custom SiPM: From BSI to TSV interconnections

Progress in 3D interconnecting technologies paved the way for a new generation of Silicon Photomultipliers (SiPM) and Single Photon Avalanche Diode (SPAD): hybrid devices which combine the integrated functionalities of the digital SiPM with the high performance of custom technologies, like low noise and high detection efficiency. Recently, Fondazione Bruno Kessler (FBK) has been working on the implementation of recently developed 3D integration technologies, on SiPMs devices, to improve both performances and functionalities by creating backside-illuminated (BSI) devices and Through Silicon Vias (TSV) interconnections.Two different technology platforms have been investigated: a BSI design for near-infrared (NIR) sensitive SiPMs and TSV interconnections for near- and vacuum-ultraviolet (NUV/VUV) sensitive detectors.For NIR applications, electrical characterization of ultra-thin (about 10μm) SiPM wafers with a metal reflector on the frontside has shown an improved photon detection efficiency (PDE) when operated in BSI configuration compared with non-thinned front-side illuminated (FSI) devices, allowing at the same time full high-segmentation access to the SiPM output from the front-side.Instead, for NUV/VUV applications, a FSI stacked approach is considered more suitable since the junction depth needs to be shallower. In this case, TSV interconnections using two different approaches (named Via-Mid and Via-Last) have been implemented allowing the placement of the contacts on the backside of the wafer.

Effective Routing Algorithm for Thermal Management in Vertically- Partially-Connected 3D-network on Chip

Introduction: The 3D integrated circuit technology, which smooths out the massive increase in transistors on a chip by stacking numerous silicon layers vertically, is quickly becoming a revolutionary technology. Thermal issues are more relevant for 3D Network-on-Chip (NoC) systems than their 2D counterparts. Methods: This paper presents a novel Vertically-Partially-Connected 3D-Network on-chip architecture that reduces the total length of interconnects and reduces the number of 3D routers. We also present an efficient XYZ routing technique for thermal management. The proposed algorithm distributes traffic based on the number of layers and congestion to achieve chip heat balancing, avoid high peak temperatures, improve average packet latency, and extend chip service life. Results: Simulation results showed that the routing technique reduces the peak temperature of the chip by an average of 17 °C compared to the exiting routing algorithms, with minimized negative impact on performance. Conclusion: Furthermore, the Vertically-Partially-Connected 3D-Network on-chip implemented in this study using VHDL exhibits improved area occupation by reducing the number of employed LUT in the FPGA compared to previous works.

(Invited) Advancing 3D Packaging for Heterogenous Systems Integration

Next generation computing architectures including those for machine learning and AI (Artificial Intelligence) have increasing demands on bandwidth, memory capacity and energy efficiency. All of which can be improved through the increased integration density offered by advanced packaging technologies. In this talk, we will provide an overview of the different 3D integration technologies and cover their scaling and application considerations. These include technologies for direct die to die connections such as advanced solder interconnects at 20 and 10 µm pitch and hybrid bonding or Foveros Direct to support increased interconnect density to below 10 µm pitch or more than 10,000 connections/mm2. The increased interconnect density can dramatically improve the bandwidth capability and energy efficiency. We will also cover some of the considerations for 3D die stacking such as thermal hot spots and power delivery constraints and how these can be addressed through design and packaging technology combinations. Finally, we will discuss some future directions to support continued performance improvement.

785-nm Frequency Comb-Based Time-of-Flight Detection for 3D Surface Profilometry of Silicon Devices

Three-dimensional integrated circuits (3D-ICs) are becoming more significant in portable devices, autonomous vehicles, and data centers. As the demand for highly integrated and high-performance semiconductor devices grows, recent 3D integration technologies focus on lowering the size of the micro-structures on such devices for high density. In order to inspect the 3D semiconductor devices, it is critical to measure the heights, depths, and overall surface profiles of the micro-structures made with silicon materials. Here, we demonstrate precise surface imaging for silicon devices by using a femtosecond mode-locked laser centered at 785 nm wavelength and an electro-optic sampling-based time-of-flight detection method with sub-10-nanometer axial precision. We could successfully measure the surface profiles as well as the step heights of silicon wafer stacks and micro-scale structures on silicon substrates.

Heterogeneous and Monolithic 3D Integration Technology for Mixed-Signal ICs

For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display, etc.) which require high-performance, small form factors, and low power consumption, heterogeneous and monolithic 3D (M3D) integration employing advanced Si CMOS technology has been intriguing. To realize the M3D-based systems, it is important to take into account the relationship between the top and bottom devices in terms of thermal budget, electrical coupling, and operability when using different materials and various processes during integration and sequential fabrication. In this paper, from this perspective, we present our recent progress of III-V devices on Si bottom devices/circuits for providing informative guidelines in RF and imaging devices. Successful fabrication of the high-performance InGaAs high electron mobility transistors (HEMTs) on the bottom ICs, with a high unity current gain cutoff frequency (fT) and unity power gain cutoff frequency (fMAX) was accomplished without substrate noise. Furthermore, the insertion of an intermediate metal plate between the top and bottom devices reduced the thermal interaction. Furthermore, the InGaAs photodetectors (PDs) were monolithically integrated on Si bottom devices without thermal damage due to low process temperature. Based on the integrated devices, we successfully evaluated the device scalability using sequential fabrication and basic readout functions of integrated circuits.

Impact of Polymer Liners on Crosstalk Induced Delay of Different TSV Shapes

The performance of a through silicon via (TSV) based 3D integrated circuit technology is primarily dependent on the choice of an appropriate liner material. The most commonly used liner material, SiO2, is undergoing considerable reliability challenges such as coefficient of thermal expansion (CTE) mismatch, scallop formation, and interfacial delamination related problems. Therefore, TSVs employed with a polymer liner have achieved significant attention in recent years due to their low dielectric constant and excellent step coverage along the via surface that can effectively reduce thermal stress and crosstalk induced delay. This paper presents a comprehensive and accurate RLGC model for different via shapes, considering the impact of various liner materials on the crosstalk induced delay. Considering an accurate via geometry and material properties at 32 and 45 nm technology, the proposed equivalent RLGC parameters include the cumulative effects of TSV metal, liner, bump, and the silicon substrate. The aforementioned parameters are used to model a novel T-type equivalent electrical network of cylindrical, tapered, and coaxial TSVs considering a coupled driver-via-load (DVL) setup. The proposed equivalent models of different via shapes are used to demonstrate the worst-case crosstalk induced delay in TSVs under the influence of various liner materials. Considering a tapered TSV, a significant improvement in crosstalk induced delay at 32 nm w.r.t. 45 nm technology is observed as 53.5%, 33.76%, and 19.12% at aspect ratios of 2.4, 3, and 4, respectively for the BCB liner.