Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs

Abstract

3D integration technology is one of the leading options to advance Moore’s Law beyond conventional scaling. One of the 3D integration choice is the heterogeneous integration with the benefits of power saving over the homogeneous integration. With the lack of commercial 3D tools, existing 3D physical design flows utilizes 2D commercial tools to perform 3D IC physical synthesis. Specifically, these flows build 2D designs first and then convert them into 3D designs. However, several works demonstrate that design qualities degrade during this 2D-3D transformation and some of the flows do not support heterogeneous integration. In this paper, we propose Snap-3D, a constraint-driven placement approach to build commercialquality 3D ICs, which supports both homogeneous and heterogeneous 3D ICs. Our key idea is based on the observation that if the standard cell height is contracted and partitioned into multiple tiers, any commercial 2D placer can place them onto the row structure and naturally achieve high-quality 3D placement. This methodology is shown to optimize power, performance, and area (PPA) metrics across different tiers simultaneously and minimize the aforementioned design quality loss. Experimental results on seven industrial designs demonstrate that Snap-3D achieves up to 10.9% wirelength, 9% power, and 25% performance improvements compared with state-of-the-art 3D design flows.