Effective Routing Algorithm for Thermal Management in Vertically- Partially-Connected 3D-network on Chip

Abstract

Introduction: The 3D integrated circuit technology, which smooths out the massive increase in transistors on a chip by stacking numerous silicon layers vertically, is quickly becoming a revolutionary technology. Thermal issues are more relevant for 3D Network-on-Chip (NoC) systems than their 2D counterparts. Methods: This paper presents a novel Vertically-Partially-Connected 3D-Network on-chip architecture that reduces the total length of interconnects and reduces the number of 3D routers. We also present an efficient XYZ routing technique for thermal management. The proposed algorithm distributes traffic based on the number of layers and congestion to achieve chip heat balancing, avoid high peak temperatures, improve average packet latency, and extend chip service life. Results: Simulation results showed that the routing technique reduces the peak temperature of the chip by an average of 17 °C compared to the exiting routing algorithms, with minimized negative impact on performance. Conclusion: Furthermore, the Vertically-Partially-Connected 3D-Network on-chip implemented in this study using VHDL exhibits improved area occupation by reducing the number of employed LUT in the FPGA compared to previous works.