3D Integration Technology Research Articles

Plug&Chip

In the embedded system domain there is a continuous demand towards providing higher flexibility for application development. This trend strives for virtual prototyping solutions capable of performing fast system simulation. Among other benefits, such a solution supports concurrent hardware/software system design by enabling to start developing, testing, and validating the embedded software substantially earlier than has been possible in the past. Towards this direction, throughout this article we introduce a new framework, named Plug&Chip, targeting to support rapid prototyping of 2D and 3D digital systems. In contrast to other relevant approaches, our solution provides higher flexibility by enabling incremental system design, while also handling platforms developed with the usage of 3D integration technology.

System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform

3D integration is being explored as a viable alternative to overcome limitations faced by mobile MPSoC platforms in traditional 2D designs. TSV based interdie connection is the most widely used approach currently. Although, TSV dimensions are scaling down, they still impose a restriction on the interdie connections density and the granularity at which 3D partitioning can be carried out. These limitations will aggravate in future scaled technologies. Alternatives such as Cu-Cu bonding need to be explored to achieve very fine-pitch and high density interdie connections. In this letter, we carry out a system architecture level comparison for a complex MPSoC platform instantiated for wireless PHY processing (WLAN and LTE). We compare 2D and 3D using: 1) TSVs with μ bump and RDL (F2B); and 2) Cu-Cu bonding (F2F). We show significant gains in 3D as compared to 2D. We also show that F2B and F2F have different system level architecture requirements, and that their impact on parameters at interconnect and system architecture level varies.

R&D Overview of 3D Integration Technology Using TSV in Japan

The electronic industry which towed Japanese industry is making a desperate effort for the second prosperity. The past several years a decline of Japanese electronic industry, especially semiconductor industry is severe and must come back again.3D Integration Technology using Thorough Si Via (TSV) is expected as the engine for strengthening of global competitiveness. This technology, as a core technology of More than Moore, that importance has been recognized and development has been performed all over the world. However, full-scale volume production is not started yet, since killer applications which can accept the higher cost are not found. But the adoption to High band memory such as HMC, HBM, Wide/IO SDR, NAND memory, FPGA products, Logic+ Memory, CIS and so on including 3D and 2.5D will be expected in the near future.In this presentation, the history of R&D of 3D Integration Technology using TSV in the world and the latest R&D are overviewed. Then, R&D results of Japanese national R&D project "Development on Functionally Innovative 3D-Integrated Circuit (Dream Chip)” which had been conducted through FY2008 to FY2012 is introduced. These consisted of six following subjects which lead to volume production were developed.-Thermal Management & Chip Stacking Technology-Thin Wafer Technology-Ultra-wide Bus SiP 3D Integration Technology-Digital-Analog 3D Integration Technology Heterogeneous 3D Integration Technology-3D-Integration Basic TechnologyMoreover, is explained the outline of "Next Generation Smart Device Project" newly started by the schedule of from FY2013 to FY2017. These are development of the key device of the system for grasping the circumference information on a car and realizing safe driving support.-In-vehicle obstacle sensing device-Obstacle detection and a risk cognition application-processor

Delamination Root Cause in Temporary Bonding

In the past few years, the More than Moore initiative has led to a focus on developing new process flows in the 3D-IC field [1-2]. One of the key points for an entire 3D integration success is being able to handle the thin wafer during backside processing reliably. Temporary bonding has emerged as one of the answers [3-4]. However, some challenges still need to be overcome in order to fully control and understand this technique.Temporary bonding is based on the use of a carrier wafer bonded to a device wafer, thanks to an adhesive layer. Depending on the temporary bonding technology used, an additional release layer or anti-sticking-layer may be added to the stack to facilitate debonding. For any technology, the temporarily bonded stack consisting of the device and the carrier wafer has to withstand the backside process flow while being easily de-bondable at the end of this process.In order to fulfill these requirements, the temporary adhesive is playing a major role: it has to demonstrate at the same time high thermal resistance (above 260°C for 30min), as well as an excellent cleanability or removability after simple de-bonding. The adhesive must also provide a means for embedding the front side topology of the device wafer while demonstrating resistance against process chemicals and exhibiting compatibility with processes requiring vacuum environments. All these criteria are difficult to match with one solution because they require different polymer properties. Thermoplastic, silicone based and polyimide based materials as well as other polymers have been investigated with respect to overcoming those challenges [5-6-7].Specifically, the delamination defect observed - most commonly with thermoplastic solutions- is an important issue remaining not fully understood. This paper aims at studying the root cause of delamination defects observed in temporary bonding, and defines which key parameters of the device or of the 3D integration process itself should be checked before selecting the temporary bonding material. Based on that, process windows for existing and new materials could be then studied regarding the key parameters defined through this work.To start, parameters which could be the possible root cause for delamination have been defined. This delamination phenomenon is occurring frequently during PECVD deposition. This deposition process is done under temperature and vacuum. Moreover, the use of plasma is creating a local increase of the temperature of the wafer. The thin device can also react to the deposition, by changing its stress or its bow during the process. Five factors are then discriminated from these observations as possible root cause (process temperature, vacuum level, thermal gradient, bow and warp, intrinsic stress). Simple test vehicles have been developed to study individually each of the five parameters listed above. At the end, some tests combining different parameters have finally shown the complex mechanism behind the delamination phenomenon.In this paper, we will present each test vehicle, the respective results and observations. At the end we will see that the combination of three parameters is leading to the delamination defect and the interaction between them will be discussed. Moreover mechanical simulation will be carried out to define numerical criteria for describing and finally avoiding such delaminations.REFERENCE[1] J. U. Knickernocker et al., “2.5D and 3D technology Challenges and Test Vehicle Demonstrations”, Proc. of Electronic Components and Technology Conference, 2012, pp.1068-1076.[2] S. Cheramy et Al., “200mm & 300mm processes & characterization for face to back flow chart for WideI/O”, Proc. of International Microelectronics And Packaging Society, 2012, pp. 8-13[3] J. Burggraf et al., “Low temperature wafer bonding for 3D applications”, Proc. of WaferBond Conference, 2013, pp. 127-128[4] T. Matthias et al., “Room temperature debonding – an enabling technology for TSV and 3D integration”, Proc. of Electronic Packaging and Technology Conference, 2012, pp. 244-247[5] A. Jouve et al., “WSS and ZoneBONDTMtemporary bonding techniques comparison for 80µm and 55µm functional interposer creation”, Proc. of Electronic Components and Technology Conference, 2013, pp. 101-106[6] K. Vial et al., “Challenges and solutions for ultra-thin (50µm) silicon using innovative ZoneBONDTMprocess”, Proc. of Electronic Packaging and Technology Conference, 2012, pp. 450-455[7] P. Montméat et al., “TTV value improvement of thin films obtained by temporary bonding ZoneBONDTM technology”, Proc. of WaferBond Conference, 2013, pp. 147-148

Surface Inspection of Cu-Cu Non-Thermal Compression Bonding for Wafer-to-Wafer 3D Stacking

Backside illuminated CMOS image sensors with a 3D stacked architecture, where the pixel array is attached on top of the logic circuit, was introduced and have just come to the market. Image sensor featuring 3D stacking was realized by connection between the interconnect layers of the top and bottom parts using vertical type through-silicon via (TSV).1 Cu bonding technology for 3D integration has been studied and widely applied.2As Wafer-to-wafer bonding process is now being used widely and matured through the production of Backside illuminated CMOS image sensors, Copper-copper bonding provides an attractive route to 3D stacked image sensor since it creates a strong metal bond and enables vertically electrical connection during the bonding process.Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers using Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. Surface preparations for the hybrid fusion bonding such as removal of Cu oxide, Cu surface protection and optimized CMP planarization patterned Cu surfaces have been studied,3 but the study on plasma condition for hybrid fusion bonding is relatively a few. The work described here is investigating of the plasma-related Cu patterned hybrid surface preparation under different plasma conditions.The main physical mechanisms about Cu-Cu non thermal compression bonding are spontaneous adhesion of hydrophilic surfaces followed by Cu diffusion across the bonding interface when Cu-Cu contact is reached (diffusion bonding) have been previously reported.4 The property of Cu dielectric diffusion barriers used in ULSI is hydrophobic. For the efficient bonding of hydrophobic-hydrophobic layers, surface conversion process is introduced.5 In the case of Cu-patterned hybrid bonding in typical Cu metallization layer in ULSI, Trade-off between dielectric diffusion barrier and Cu cannot be avoidable by surface conversion process.During the Cu-patterned hybrid bonding development, the common electrical failed areas were found.To investigate the failure mechanism, influence of plasma condition on the activation of wafer surface and bonding quality was studied. The wafer surface was examined by X-ray photoelectron spectroscopy (XPS), surface roughness, and observation of differential work function uniformity over a full wafer area caused by plasma-induced charge.6The ChemetriQ NVD inspection system from Qcept Technologies was used to inspect differential work function uniformity.After implementing plasma treatment applied in bonding process, Non-uniformity of a charge map and different plasma influence over a full wafer area were shown, even there was no difference through the AFM analysis. For the optimization of the bonding process, especially plasma process, a method to examine the surface condition in this paper makes it possible to monitor the plasma process and improve bonding process

Advances in Wafer Bonding for 3D Integration and Other Applications

Bonding is one of the key technologies that enable the 3D integration. 3D integration has more choices in terms of 3D process flows, such as chip-on-chip (CoC), chip-on-wafer (CoW) or wafer-on-wafer (WoW). Bonding process can be used to glue multiple functional IC chips vertically and provide some combinations of mechanical, thermal, electrical and optical connections between chips or wafers permanently, or to provide temporary mechanical support for wafer thinning and thinned wafer handling. Bonding process also varies with different materials and applications. The choice of bonding technology depends on combinations of the chips and their required process conditions such as temperature limitations. This invited talk focuses on advances in bonding technologies for 3D integration and other applications, including different bonding approaches, requirements for materials and processes, bonding quality characterizations and application-specific bonding technologies.

3D Wafer Level Heterogeneous Integration

3D integration is worldwide considered as one of the most important key technology for microelectronics to meet the growing demands regarding more functionality with concurrent increase in performance as well as miniaturization and cost reduction. So 3D integration is of main relevance for application areas e.g. cyber physical systems, internet of things, ambient assisted living (AAL) as well as information & communication, logistics, security, automotive, health care and industrial electronics. Besides following “More Moore”, Europe is pursuing a strategy on heterogeneous integration approaches following “More than Moore”. In this context, individual and different 3D integration approaches are adapted to the specific application scenarios.Interposers with Through Silicon Vias (TSV) are becoming a very important element for the realization of 3D System in Packages (SiPs). Main advantages of silicon interposers are the decoupling of front end/back end processing for the implementation of TSVs, redistribution layers (RDL) and the integration of active and passive devices. Besides independent manufacturing, interposers can be realized in short time-to-market time frame and in a cost effective way. TSV interposers are designed and manufactured for the different application areas which results also in different technical specifications ranging from high density TSV integration and high density RDL for digital applications to interposers for RF application as well as MEMS integration and optical interconnects.The presentation will highlight results and technical achievements for 3D integration using TSV interposer and addresses as well the broad spectrum of topics from design, technology and reliability related to 3D systems.Concerning technical features, interposers deal with high density wiring redistribution layers (RDL), TSVs and top/bottom side interconnect formation (bumping). This allows the electrical signal routing across the top side and to the interposer back side. Some new applications appear to require up to 4 layers RDL of less than 1μm line/space and silicon oxide/nitride dielectric layer.Silicon interposers with TSVs provide additional features to address 3D-SiP for heterogeneous integration. These include:Device carrier for stacked devices,High density wiring between (stacked) components,3D device stacking using TSVs,Integrated passive devicesEmbedding of active devices into the IP,Functional layer integration (actors, sensors, antennas),Modularization,Integrated test features For the assembly and 3D stack formation of the devices, different interconnection technologies, e.g. micro solder bumps (SnAg) and copper pillars, are used to deal especially with surface topography of the devices and warpage of the board/substrate.Beside silicon interposer, also glass interposers are emerging elements for specific applications. Compared to silicon interposers, glass interposer currently have only limited via dimension and cannot deal with high density TSVs, e.g. <5µm diameter and 10µm pitch. For this, the supply chain is still emerging. The metallization process for silicon interposers is commonly established in wafer fabs. However, most of these facilities do not possess via-last or bumping capability. SUMMARY 3D integration technology is one of the main drivers in packaging and system integration to meet the requirements for high functionality, highly miniaturized smart systems.Future advanced 3D systems will result in complex 3D stacking approaches using the TSV technology. Silicon interposers with TSVs are an important element to combine different advanced devices into one miniaturized system (SiP) with high functionality and to overcome currently existing issues regarding TSV integration into active devices. One important task is the supply chain between e.g. IDMs, OSAT or packing houses.Another crucial aspect is the balance between performance improvement and 3D manufacturing cost (TSV & packaging). So the implementation of 3D integration using TSV and interposer is very product specific. 3D integration requires, beside the technology approaches, also an overall SiP process integration approach which addresses design, technology and reliability.Fraunhofer IZM’s center “All Silicon System Integration Dresden - ASSID” and the Fraunhofer Cluster 3D Integration (http://www.3d-integration.fraunhofer.de/en.html) are focusing on the development and prototyping of 3D systems using Cu-TSVs in active devices (via middle, via last) and silicon interposers as well.

Interview

Dr Dingyou Zhang of GLOBALFOUNDRIES talks about her research interests and the paper ‘BMD Impact on Silicon Fin Defect at TSV Bottom’, page 954. Dr Dingyou Zhang As the semiconductor industry strived to scale according to Moore's Law, the conventional planar ICs encountered many physical, technological and economic bottlenecks. 3D integration technology, by stacking and connecting function blocks in a vertical fashion, promises to alleviate such bottlenecks and has been widely investigated in recent years. The potential benefits of 3D integration include multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. Performance improvement in 3D ICs is mainly due to reduction of interconnect length reducing interconnect delay and power consumption. Small form factor is achieved by stacking active device layers on top of one another. During my M.S. and Ph.D. I was working on several research topics related to 3D integration, including TSV thermal-mechanical reliability and a novel chip-to-wafer 3D integration approach. I joined GLOBALFOUNDRIES in 2013 and I am currently working on advanced packaging technologies in the office of the CTO, focusing on through-silicon via (TSV) technology. The TSV is an important enabling component in 3D integration; electrically connecting multiple strata of ICs using short vertical vias that pass through a thinned silicon wafer substrate in order to establish a connection between the active side and backside of the die. Compared to conventional wirebonding and flipchip stacking, TSVs enable high-performance, high functionality, compact heterogeneous systems with high data bandwidth and speed, and low power requirements by providing the shortest interconnect path and higher interconnect density, compactly. However, it is challenging to fabricate reliable TSVs and substantial research is being conducted on aspects including their design, processing materials, metrology development and thermal-mechanical reliability. We report a recently found silicon fin defect at TSV bottom which was identified as a killer defect. To examine the root cause of this defect, we explored different inspection options and finally developed an effective method to catch the defect post TSV deep reactive ion etch. This is compatible with inline inspection and can be easily verified by cross-sectioning the via. With this well-established inspection approach, we were able to further investigate various potential root causes of the defect, such as TSV density microloading, TSV location and photoresist residue impacts. After ruling out other effects, bulk micro defect (BMD) turned out to be a key root cause; based on both BMD simulation and experimental results. Thus a low BMD or non-BMD silicon substrate is recommended to reduce or eliminate this defect. The work provides a viable way to clear this roadblock for TSV manufacturability. This is a killer defect which is hard to detect due to its deep location at the bottom of high aspect ratio vias, it can cause yield loss and requires elimination. We have seen mechanical failures caused by this defect after assembling TSV chips. One example we show is a silicon fin defect at TSV bottom causing copper diffusion into silicon cracks in TSV vicinity, after wafer thinning and TSV backside reveal process. A desirable inspection point for using our SEM automatic process inspection is right after TSV etch. Post etch is the first step in which we found this silicon fin defect and it saves downstream manufacturing resources from processing defective TSVs. Post etch inspection results can be easily verified physically and correlated to silicon fin defects, since TSVs are not filled with metal yet. This inspection approach can be adopted after TSV etch and before photoresist ashing and clean, which has less Q time concerns than between TSV post etch clean and dielectric liner deposition. 3D integration is predicted to be a key technology to solve performance and cost problems of conventional IC fabrication in the ITRS roadmap, which will probably be based on TSV technology. Full 3D process flows have already been demonstrated with no major showstoppers from a design or process point of view. While cost reduction is still on the to-do list for high volume production, multiple equipment and material suppliers are focusing on optimising processes to lower costs. With a positive outlook for commercialisation, a strong demand for such future 3D IC applications including memories and processors is expected in the next few years.

Development and applications of 3-dimensional integration nanotechnologies.

Unlike conventional two-dimensional (2D) planar structures, signal or power is supplied through through-silicon via (TSV) in three-dimensional (3D) integration technology to replace wires for binding the chip/wafer. TSVs have becomes an essential technology, as they satisfy Moore's law. This 3D integration technology enables system and sensor functions at a nanoscale via the implementation of a highly integrated nano-semiconductor as well as the fabrication of a single chip with multiple functions. Thus, this technology is considered to be a new area of development for the systemization of the nano-bio area. In this review paper, the basic technology required for such 3D integration is described and methods to measure the bonding strength in order to measure the void occurring during bonding are introduced. Currently, CMOS image sensors and memory chips associated with nanotechnology are being realized on the basis of 3D integration technology. In this paper, we intend to describe the applications of high-performance nano-biosensor technology currently under development and the direction of development of a high performance lab-on-a-chip (LOC).

High-Yield Fabrication Process for 3D-Stacked Ultrathin Chip Packages Using Photo-Definable Polyimide and Symmetry in Packages

Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach. Initially, thinned dies are embedded in a polyimide interposer with a fine-pitch metal fanout, resulting in ultrathin chip packages (UTCPs). Next these UTCPs are stacked by lamination. Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by the introduction of an additional layer of interposer, which makes it flat at the chip edge and thus the whole package is named as flat-UTCP. In addition to that, randomness in nonfunctional package positions per panel reduces the overall yield of the whole process up to a certain extent. A detailed analysis on these two issues to improve the process yield is presented in this paper. 3D-stacked memory module composed of four electrically erasable programmable read-only memory dies was processed and tested to demonstrate this new concept for enhancing the fabrication yield.

TSV technology embedding high density capacitors for Advanced 3D packaging solutions

TSV is one of the key technologies for 3D integration . TSVs co-integrated with passives including high density capacitors enable highly integrated heterogeneous solutions required because of the smaller size of the electronic modules . Even if there is still a lot to do , significant progress has already been done on the process , on the testability , on the performances of these smart interposers .The major progress is in the adoption of the technology .In this paper we'll expose some examples where the adoption was driven by cost, performances &amp; miniaturization. Emphasis will be placed on the performances of the new generation of 3D Silicon capacitors, using key enabling technology like ALD and amazing architecture that allow impressive capacitance density increase.

Temporary Wafer Bonding and Debonding for 3D Integration Using an Electrochemically Active Polymer Adhesive

The use of thin silicon wafers is an enabling technology for 3D integration in the semiconductor industry. However, thin silicon wafers are fragile to handle and reliable solutions are required for thin wafer handling. This paper reports a novel method of bonding and debonding a thin wafer (<50 μm) using an electrochemically active polymer adhesive. In the presented method the carrier wafer is first spin coated with the adhesive and then bonded to the device wafer by applying force and temperature. Debonding of the wafer is realized at room temperature by applying a voltage between the carrier and the device wafer, which substantially reduces the bond strength. The bonding and debonding properties of the adhesive show that temporary wafer bonding using electrochemically active adhesives has the potential to be an attractive approach for temporary wafer bonding for thin wafer handling in 3D integration processes.

2.5D and 3D Integration Technology Update

This publication will cover Tezzaron's latest advancements in 2.5D and 3D technology including new wafer to wafer integration of InP and GaAs with CMOS devices and new work in bonded die to wafer assembly with sub 25um pitch. A manufacturing perspective of the evolving customer requirements and the unique challenges in testing these highly complex devices will be discussed.

Electrical characteristics and thermal shock properties of Cu-filled TSV prepared by laser drilling

The electrical characteristics and thermal shock properties of a Through Silicon Via (TSV) for the three dimensional (3D) stacking of a Si wafer were investigated. The TSVs were fabricated on a Si wafer by a laser drilling process. The via had a diameter of 75 µm at the via opening and a depth of 150 µm. A daisy chain was made for testing electrical characteristics, such as Rsh (sheet resistance), Rc (contact resistance) and Z0 (characteristic impedance). After Cu filling, a cross section of the via was observed by Field Emission-Scanning Electron Microscopy. The electrical characteristics were measured using a commercial impedance analyzer and probe station, which revealed the values of Rsh, Rc and Z0 as 35.5 mΩ/sq, 25.4 mΩ and 48.5 Ω, respectively. After a thermal shock test of 500 cycles, no cracks were observed between the TSV and Si wafer. This study confirms that the laser drilling process is an effective method for via formation on a Si wafer for 3D integration technology.

(Invited) Challenges in 3D Integration

Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.

Experience with 3D integration technologies in the framework of the ATLAS pixel detector upgrade for the HL-LHC

3D technologies are investigated for the upgrade of the ATLAS pixel detector at the HL-LHC. R&D focuses on both, IC design in 3D, as well as on post-processing 3D technologies such as Through Silicon Via (TSV). The first one uses a so-called via first technology, featuring the insertion of small aspect ratio TSV at the pixel level. As discussed in the paper, this technology can still present technical challenges for the industrial partners. The second one consists of etching the TSV via last. This technology is investigated to enable 4-side abuttable module concepts, using today's pixel detector technology. Both approaches are presented in this paper and results from first available prototypes are discussed.

Localized Temperature Stability in Low‐Temperature Cofired Ceramics

Low‐temperature cofired ceramic (LTCC) is a multilayer 3D packaging, interconnection, and integration technology. For LTCC modules targeting radio and microwave frequency (RF and MW) applications, a low or near 0 ppm/°C temperature coefficient of resonant frequency (τf) ensures temperature stability of embedded resonator and filter functions. The base dielectrics of most commercial LTCC systems have a τf in the range −50 to −80 ppm/°C. This study explored a method to achieve a zero τf on stripline (SL) resonators by locally cofiring, in a multilayer LTCC structure, compensating dielectrics (CD) with an opposite τf to that of the host dielectric. The formulation, synthesis, dielectric properties, and microstructure of SrTiO3 (STO)‐based low‐fire τf CD are presented. Chemical interactions and physical compatibility between the compensating and the host LTCC dielectrics are investigated for cofireability. The dependence of τf compensation on the wt% of STO, the printed thickness, and the location of the CD in multilayer LTCC are discussed. The most effective τf compensation is achieved by integrating CD next to the resonator lines, and can be explained by the concentration of electromagnetic energy via total internal reflection of electromagnetic waves inside the CD layer.

Electrical characterization of integrated passive devices using thin film technology for 3D integration

With the development of 3D integration technology, microsystems with vertical interconnects are attracting attention from researchers and industry applications. Basic elements of integrated passive devices (IPDs), including inductors, capacitors, and resistors, could dramatically save the footprint of the system, optimize the form factor, and improve the performance of radio frequency (RF) systems. In this paper, IPDs using thin film built-up technology are introduced, and the design and characterization of coplanar waveguides (CPWs), inductors, and capacitors are presented.

A hierarchical vision processing architecture oriented to 3D integration of smart camera chips

This paper introduces a vision processing architecture that is directly mappable on a 3D chip integration technology. Due to the aggregated nature of the information contained in the visual stimulus, adapted architectures are more efficient than conventional processing schemes. Given the relatively minor importance of the value of an isolated pixel, converting every one of them to digital prior to any processing is inefficient. Instead of this, our system relies on focal-plane image filtering and key point detection for feature extraction. The originally large amount of data representing the image is now reduced to a smaller number of abstracted entities, simplifying the operation of the subsequent digital processor. There are certain limitations to the implementation of such hierarchical scheme. The incorporation of processing elements close to the photo-sensing devices in a planar technology has a negative influence in the fill factor, pixel pitch and image size. It therefore affects the sensitivity and spatial resolution of the image sensor. A fundamental tradeoff needs to be solved. The larger the amount of processing conveyed to the sensor plane, the larger the pixel pitch. On the contrary, using a smaller pixel pitch sends more processing circuitry to the periphery of the sensor and tightens the data bottleneck between the sensor plane and the memory plane. 3D integration technologies with a high density of through-silicon-vias can help overcome these limitations. Vertical integration of the sensor plane and the processing and memory planes with a fully parallel connection eliminates data bottlenecks without compromising fill factor and pixel pitch. A case study is presented: a smart vision chip designed on a 3D integration technology provided by MIT Lincoln Labs, whose base process is 0.15@mm FD-SOI. Simulation results advance performance improvements with respect to the state-of-the-art in smart vision chips.

Advanced wafer thinning technology and feasibility test for 3D integration

The ultra-thinning less than [email protected] of total thickness variation (TTV) within 300mm wafer has been developed for the wafer-on-a-wafer (WOW) application. TTV was controlled by measuring wafer thickness and parallelity between grinder and wafer surface, called Auto-TTV method. Surface treatment to remove damage layer such as defects and non-crystalline layer was also developed. For the ultra-thinning less than [email protected] in wafer thickness, no significant device degradation in the high performance 45nm node CMOS and FRAM memory was revealed. The impact of ultra-thinning processes on strained transistors and Cu/low-k multilevel interconnects as well as FRAM memory is described. Properties examined include stack chain resistance of [email protected] interconnects as well as Ion-Ioff, threshold voltage shift, and junction leakage of transistors for CMOS logic, and switching characteristics for FRAM before and after thinning. It was found that the electrical properties were not affected by bonding, thinning and debonding process, indicating good feasibility of 3D stacking integration.